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STM32G071EBY3TR (WLCSP-25(2.3x2.5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32G071EBY3TR

STID: C724079WLCSP-25(2.3x2.5) · 25 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32G071EBY3TR (WLCSP-25(2.3x2.5))A1PA15A2PA14BOOT0 -A3PB5A4PB7A5PC14 - OSC32B1PA12 [PA10]B2PA13B3PB6B4PB8B5IOB5C1PA11 [PA9]C2PA6C3PA3E5PF2 NRST -E4PA2E3PA5E2PB0E1PB1D5VSS/VSSAD4PA1D3PA4D2PA7D1PA8C5VDD/VDDAC4PA0Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.822.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
A1A2A3A4A5B1B2B3B4B5C1C2C3C4C5D1D2D3D4D5E1E2E3E4E5E=2.30mm · Pitch e=0.40mmD=2.50mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.30mm × 2.50mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (25/25)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PA15I/OMultiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)
A2PA14BOOT0 -I/OMultiplexed I/O & Peripheral Pin PA14BOOT0 - (UART, SWD/JTAG)
A3PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, PWM)
A4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART)
A5PC14 - OSC32_IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)
B1PA12 [PA10]I/OMultiplexed I/O & Peripheral Pin PA12 [PA10] (UART, SPI, I2C)
B2PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
B3PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART)
B4PB8I/OMultiplexed I/O & Peripheral Pin PB8 (SPI)
B5IOB5I/OGeneral Purpose Digital I/O Pin IOB5
C1PA11 [PA9]I/OMultiplexed I/O & Peripheral Pin PA11 [PA9] (UART, SPI)
C2PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC, PWM)
C3PA3I/OMultiplexed I/O & Peripheral Pin PA3 (SPI, PWM)
C4PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, SPI, PWM)
C5VDD/VDDAPowerPower Supply Input (VDD/VDDA — 3.3V VDD (Max 4.0V))
D1PA8I/OMultiplexed I/O & Peripheral Pin PA8 (SPI, PWM, RTC/CLK)
D2PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
D3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, ADC, RTC/CLK)
D4PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, SPI, PWM)
D5VSS/VSSAGNDGround Reference Pin (VSS/VSSA)
E1PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, PWM)
E2PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC, PWM)
E3PA5I/OMultiplexed I/O & Peripheral Pin PA5 (UART, SPI, ADC, PWM)
E4PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, SPI)
E5PF2 NRST -I/OMultiplexed I/O & Peripheral Pin PF2 NRST - (RTC/CLK)
PIN A1 PA15
I/O
Multiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)
Design note: Alt: SPI1 NSS/I2S1_WS_ , USART2_RX , TIM2_CH1ETR_ , USART4_RTSDECK__ , USART3_RTSDECK__ , EVENTOUT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 20 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32G071EBY3TR (ST · WLCSP-25(2.3x2.5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) - 2. Standard Pinout (Top View)
True package pinout (25 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) - 4. Package Dimensions (D×E×A)
WLCSP-25(2.3x2.5) · 2.30×2.50mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (25 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (20 figures · Page 1/2)
Showing 1–12 of 20 uncropped original figures for STM32G071
P1 · p01_fig01EXACT PACKAGE
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) — Arm® Cortex®-M0+ 32-bit MCU, up to 128 KB Flash, 36 KB RAM,
Arm® Cortex®-M0+ 32-bit MCU, up to 128 KB Flash, 36 KB RAM,
P1 · p01_fig02EXACT PACKAGE
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) — 5 × 5 mm
5 × 5 mm
P40 · p40_fig01EXACT PACKAGE
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) — Figure 9. STM32G071GxU UFQFPN28 pinout
Figure 9. STM32G071GxU UFQFPN28 pinout
P40 · p40_fig02EXACT PACKAGE
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) — Figure 10. STM32G071Ex WLCSP25 pinout
Figure 10. STM32G071Ex WLCSP25 pinout
P126 · p126_fig01EXACT PACKAGE
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) — Figure 53. WLCSP25 chip-scale package outline
Figure 53. WLCSP25 chip-scale package outline
P127 · p127_fig01EXACT PACKAGE
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) — Figure 54. Recommended PCB pad design for WLCSP25 package
Figure 54. Recommended PCB pad design for WLCSP25 package
P1 · p01_fig02P1
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P37 · p37_fig011546×1111px
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) — Figure 4. STM32G071RxI UFBGA64 pinout 1 2 3 4 5 6 7 8
Figure 4. STM32G071RxI UFBGA64 pinout 1 2 3 4 5 6 7 8
P37 · p37_fig021546×915px
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) — Figure 5. STM32G071CxT LQFP48 pinout
Figure 5. STM32G071CxT LQFP48 pinout
P38 · p38_fig011546×859px
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) — Figure 6. STM32G071CxU UFQFPN48 pinout
Figure 6. STM32G071CxU UFQFPN48 pinout
P38 · p38_fig021546×1430px
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) — Figure 7. STM32G071KxT LQFP32 pinout
Figure 7. STM32G071KxT LQFP32 pinout
P53 · p53_fig011548×1316px
STM32G071EBY3TR (WLCSP-25(2.3x2.5)) — Figure 13. Power supply scheme
Figure 13. Power supply scheme
Page 1 / 2 (20 extracted figures)

Technical Specifications & Part Details (STM32G071EBY3TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32G071EBY3TR (WLCSP-25(2.3x2.5)) is a 25-pin embedded microcontroller unit (mcu) featuring a 2.50 × 2.30 × 0.56 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.62 V - 3.6 V supply operation across -40°C to 85°C with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.62 V - 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
64 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
21 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
2.50 × 2.30 × 0.56 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-25(2.3x2.5))
Pin Count & Lead PitchN / e
25 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PA14BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol25 auto-grouped pins
OK
IPC-7351B Land Pattern25 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-25(2.3x2.5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.50 × 2.30 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.25 × 0.25 mm
Pins / Total PadsTopology
25P / 25Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-25(2.3x2.5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32G071EBY3TR (WLCSP-25(2.3x2.5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32G071EBY3TR (WLCSP-25(2.3x2.5))?

Manufactured by ST, the STM32G071EBY3TR is housed in a WLCSP-25(2.3x2.5) package with 25 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.62 V - 3.6 V. Key pins include: A1 (PA15: Multiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)), A2 (PA14BOOT0 -: Multiplexed I/O & Peripheral Pin PA14BOOT0 - (UART, SWD/JTAG)), A3 (PB5: Multiplexed I/O & Peripheral Pin PB5 (SPI, PWM)), A4 (PB7: Multiplexed I/O & Peripheral Pin PB7 (UART)), A5 (PC14 - OSC32_IN (PC14): Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)), B1 (PA12 [PA10]: Multiplexed I/O & Peripheral Pin PA12 [PA10] (UART, SPI, I2C)).

What are the IPC-7351B PCB Footprint dimensions for STM32G071EBY3TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32G071EBY3TR (WLCSP-25(2.3x2.5)) has a nominal body envelope of 2.30 × 2.50 mm, pitch e = 0.40 mm, and 25 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32G071EBY3TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32G071EBY3TR (ST, WLCSP-25(2.3x2.5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (25 pins) & STM32G071 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, PWM.
A2PA14BOOT0 -Digital_IOSignal terminal PA14BOOT0 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14BOOT0 -. Supported peripheral buses: UART, SWD/JTAG.
A3PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, PWM.
A4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART.
A5PC14 - OSC32_IN (PC14)Digital_IOSignal terminal PC14 - OSC32_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN (PC14). Supported peripheral buses: RTC/CLK.
B1PA12 [PA10]Digital_IOSignal terminal PA12 [PA10] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI, I2C.
B2PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
B3PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART.
B4PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI.
B5IOB5Digital_IOGeneral Purpose Digital I/O Pin IOB5
C1PA11 [PA9]Digital_IOSignal terminal PA11 [PA9] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI.
C2PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC, PWM.
C3PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOUSART2RX. Supported peripheral buses: SPI, PWM.
C4PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKUSART2CTS. Supported peripheral buses: UART, SPI, PWM.
C5VDD/VDDAPower_InPrimary positive power supply input (VDD/VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D1PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI, PWM, RTC/CLK.
D2PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
D3PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI2_MOSITIM14CH1. Supported peripheral buses: SPI, ADC, RTC/CLK.
D4PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, PWM.
D5VSS/VSSAGND0V electrical ground return terminal (VSS/VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
E1PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, PWM.
E2PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, PWM.
E3PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, ADC, PWM.
E4PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI.
E5PF2 NRST -Digital_IOSignal terminal PF2 NRST - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF2 NRST -. Supported peripheral buses: RTC/CLK.
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