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dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

dsPIC33FJ128GP802T-I/MM

MICROCHIPQFN-28-EP(6x6) · 29 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6))1IO12IO233V34NC5VSS6OSC1/CLKI/CN7NC8IO09IO410VDD11IO612IO713IO1514IO1615IO1729EP28AN1/VREF-/CN27AN0/VREF+/CN26MCLR#25AVDD24AVSS23IO1222IO1121IO1020IO919IO2018IO1917VCAP16VSSGrid Pitch = 2.54mm (IEEE-315)-20.3-15.2-10.2-5.105.110.215.220.325.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=6.00mm · Pitch e=0.65mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1IO1I/OGeneral Purpose Digital I/O Pin IO1
2IO2I/OGeneral Purpose Digital I/O Pin IO2
33V3Power3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4NCNCNo Connect (Leave Floating)
5VSSGNDGround Reference Pin (VSS)
6OSC1/CLKI/CN30/RA2I/OMultiplexed I/O & Peripheral Pin OSC1/CLKI/CN30/RA2 (RTC/CLK)
7NCNCNo Connect (Leave Floating)
8IO0I/OGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9IO4I/OGPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10VDDPowerPower Supply Input (VDD — 3.0V to 3.6V)
11IO6I/OGPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12IO7I/OGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13IO15I/OGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14IO16I/OGPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15IO17I/OGPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16VSSGNDGround Reference Pin (VSS)
17VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
18IO19I/OGPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19IO20I/OGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20IO9I/OGPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
21IO10I/OGPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22IO11I/OGPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23IO12I/OGPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24AVSSGNDGround Reference Pin (AVSS)
25AVDDPowerPower Supply Input (AVDD — 3.0V to 3.6V)
26MCLR#I/OMultiplexed I/O & Peripheral Pin MCLR# (General)
27AN0/VREF+/CN2/RA0AnalogMultiplexed I/O & Peripheral Pin AN0/VREF+/CN2/RA0 (General)
28AN1/VREF-/CN3/RA1AnalogMultiplexed I/O & Peripheral Pin AN1/VREF-/CN3/RA1 (General)
29EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 IO1
I/O
General Purpose Digital I/O Pin IO1
Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.
IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
1. Realistic 3D PackageREPRESENTATIVE
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) - 4. Package Dimensions (D×E×A)
QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for DSPIC33FJ128 / DSPIC33FJ64G
P1 · p01_fig01376×200px
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) — 16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Advanced Analog
16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Advanced Analog
P71 · p71_fig011625×913px
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) — dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
P71 · p71_fig021777×1030px
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) — FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS
FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS
P72 · p72_fig01867×655px
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) — Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished.
Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished.
P72 · p72_fig021783×380px
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) — EQUATION 5-1: PROGRAMMING TIME | For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN<5:0> bits (see Register 9-4) are set to ‘b111111, the minimum row write time is equal to Equation 5-2. | 5.5.1 KEY
EQUATION 5-1: PROGRAMMING TIME | For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN<5:0> bits (see Register 9-4) are set to ‘b111111, the minimum row write time is equal to Equation 5-2. | 5.5.1 KEY
P165 · p165_fig011478×506px
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) — 11.8.1 KEY RESOURCES | • Section 10. “I/O Ports” (DS70193) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools | Note: In the event you are n
11.8.1 KEY RESOURCES | • Section 10. “I/O Ports” (DS70193) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools | Note: In the event you are n
P319 · p319_fig01867×890px
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) — FIGURE 27-1: CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1,2,3)
FIGURE 27-1: CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1,2,3)
P319 · p319_fig01P319
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) — Datasheet Page 319 (p319_fig01)
Datasheet Page 319 (p319_fig01)
P407 · p407_fig011777×2604px
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) — dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
P412 · p412_fig011777×2323px
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) — dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 | 28-Lead Plastic Quad Flat, No Lead Package (MM) - 6x6x0.9 mm Body [QFN-S] with 0.40 mm Contact Length | Note: For the most current package drawings, please see the Micr
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 | 28-Lead Plastic Quad Flat, No Lead Package (MM) - 6x6x0.9 mm Body [QFN-S] with 0.40 mm Contact Length | Note: For the most current package drawings, please see the Micr
P412 · p412_fig01P412
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) — Datasheet Page 412 (p412_fig01)
Datasheet Page 412 (p412_fig01)
P414 · p414_fig011777×2341px
dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) — DS70292G-page 414 © 2007-2012 Microchip Technology Inc.
DS70292G-page 414 © 2007-2012 Microchip Technology Inc.

Technical Specifications & Part Details (dsPIC33FJ128GP802T-I/MM)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 0.90 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 3.0V to 3.6V supply operation across -40°C to +125°C with integrated UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +125°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
7.37 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(6x6))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteEPAD 4.70×4.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — DSPIC33FJ128 / DSPIC33FJ64G (3)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.65mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28-EP(6x6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the dsPIC33FJ128GP802T-I/MM is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (VSS: Ground Reference Pin (VSS)), 6 (OSC1/CLKI/CN30/RA2: Multiplexed I/O & Peripheral Pin OSC1/CLKI/CN30/RA2 (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for dsPIC33FJ128GP802T-I/MM?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), dsPIC33FJ128GP802T-I/MM (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for dsPIC33FJ128GP802T-I/MM?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for dsPIC33FJ128GP802T-I/MM (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & DSPIC33FJ128 / DSPIC33FJ64G Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1IO1Digital_IOGeneral Purpose Digital I/O Pin IO1
2IO2Digital_IOGeneral Purpose Digital I/O Pin IO2
33V3Power_In3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4NCNo_ConnectNo Connect (Leave Floating)
5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6OSC1/CLKI/CN30/RA2Digital_IOSignal terminal OSC1/CLKI/CN30/RA2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC1/CLKI/CN30/RA2. Supported peripheral buses: RTC/CLK.
7NCNo_ConnectNo Connect (Leave Floating)
8IO0Digital_IOGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9IO4Digital_IOGPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10VDDPower_InPrimary positive power supply input (VDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
11IO6Digital_IOGPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12IO7Digital_IOGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13IO15Digital_IOGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14IO16Digital_IOGPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15IO17Digital_IOGPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17VCAPDigital_IOSignal terminal VCAP (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
18IO19Digital_IOGPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19IO20Digital_IOGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20IO9Digital_IOGPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
21IO10Digital_IOGPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22IO11Digital_IOGPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23IO12Digital_IOGPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24AVSSGND0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
25AVDDPower_InPrimary positive power supply input (AVDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
26MCLR#Digital_IOSignal terminal MCLR# (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General.
27AN0/VREF+/CN2/RA0AnalogSignal terminal AN0/VREF+/CN2/RA0 (Analog, 3.0V to 3.6V domain). Multiplexed alternate functions: AN0/VREF+/CN2/RA0. Supported peripheral buses: General.
28AN1/VREF-/CN3/RA1AnalogSignal terminal AN1/VREF-/CN3/RA1 (Analog, 3.0V to 3.6V domain). Multiplexed alternate functions: AN1/VREF-/CN3/RA1. Supported peripheral buses: General.
29EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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