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CH372C (SSOP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH372C

WCHID: C5301766SSOP-20 · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH372C (SSOP-20)1INT#2WR#3RD#4A05V36UD+7UD-8XI9XO10D020VCC19CS#18GND17D716D615D514D413D312D211D1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=5.30mm · Pitch e=0.65mmD=7.20mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 5.30mm × 7.20mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1INT#I/OMultiplexed I/O & Peripheral Pin INT# (General)
2WR#I/OMultiplexed I/O & Peripheral Pin WR# (General)
3RD#I/OMultiplexed I/O & Peripheral Pin RD# (General)
4A0I/OMultiplexed I/O & Peripheral Pin A0 (General)
5V3PowerRegulated Power Output (V3 — 3.3V to 5V)
6UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
7UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
8XII/OXI (RTC/CLK)
9XOI/OXO (RTC/CLK)
10D0I/OMultiplexed I/O & Peripheral Pin D0 (General)
11D1I/OMultiplexed I/O & Peripheral Pin D1 (General)
12D2I/OMultiplexed I/O & Peripheral Pin D2 (General)
13D3I/OMultiplexed I/O & Peripheral Pin D3 (General)
14D4I/OMultiplexed I/O & Peripheral Pin D4 (General)
15D5I/OMultiplexed I/O & Peripheral Pin D5 (General)
16D6I/OMultiplexed I/O & Peripheral Pin D6 (General)
17D7I/OMultiplexed I/O & Peripheral Pin D7 (General)
18GNDGNDGround Reference Pin (GND)
19CS#I/OMultiplexed I/O & Peripheral Pin CS# (General)
20VCCPowerPower Supply Input (VCC — 3.3V to 5V)
PIN 1 INT#
I/O
Multiplexed I/O & Peripheral Pin INT# (General)
Design note: 中断请求输出 低电平有效 ，
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH372C (WCH · SSOP-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH372C (SSOP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH372C (SSOP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH372C (SSOP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH372C (SSOP-20) - 4. Package Dimensions (D×E×A)
SSOP-20 · 5.30×7.20mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH372C (SSOP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH372C (SSOP-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH372
P1 · p01_fig011680×1014px
CH372C (SSOP-20) — CH372 内置了USB 通讯中的底层协议，具有省事的内置固件模式和灵活的外置固件模式。在内置 固件模式下，CH372 自动处理默认端点0 的所有事务，本地端单片机只要负责数据交换，所以单片机 程序非常简洁。在外置固件模式下，由外部单片机根据需要自行处理各种USB 请求，从而可以实现符 合各种USB 类规范的设备。 | 2、特点 | CS# | INT# | D- | D+ | WR# RD# A0 | D [7-0] | CH372 接口芯片 | 本地端 控制器 | 单片机
CH372 内置了USB 通讯中的底层协议，具有省事的内置固件模式和灵活的外置固件模式。在内置 固件模式下，CH372 自动处理默认端点0 的所有事务，本地端单片机只要负责数据交换，所以单片机 程序非常简洁。在外置固件模式下，由外部单片机根据需要自行处理各种USB 请求，从而可以实现符 合各种USB 类规范的设备。 | 2、特点 | CS# | INT# | D- | D+ | WR# RD# A0 | D [7-0] | CH372 接口芯片 | 本地端 控制器 | 单片机
P2 · p02_fig01434×434px
CH372C (SSOP-20) — 封装形式 塑体宽度 引脚间距 封装说明 订货型号
封装形式 塑体宽度 引脚间距 封装说明 订货型号
P2 · p02_fig01P2
CH372C (SSOP-20) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P12 · p12_fig011236×581px
CH372C (SSOP-20) — 8.2. 连接USB 总线/内置时钟（下图）
8.2. 连接USB 总线/内置时钟（下图）
P12 · p12_fig02998×510px
CH372C (SSOP-20) — 如果使用内置时钟的CH372C 芯片，那么可以免去外部晶体及振荡电容，电路更简洁。
如果使用内置时钟的CH372C 芯片，那么可以免去外部晶体及振荡电容，电路更简洁。
P13 · p13_fig011111×705px
CH372C (SSOP-20) — CH372 芯片具有通用的被动并行接口，可以直接连接多种单片机、DSP、MCU 等。在普通的MCS-51 系列单片机的典型应用电路中，CH372 芯片可以通过8 位被动并行接口的D7～D0、-RD、-WR、-CS、 A0 直接挂接到单片机U2 的系统总线上。
CH372 芯片具有通用的被动并行接口，可以直接连接多种单片机、DSP、MCU 等。在普通的MCS-51 系列单片机的典型应用电路中，CH372 芯片可以通过8 位被动并行接口的D7～D0、-RD、-WR、-CS、 A0 直接挂接到单片机U2 的系统总线上。
P13 · p13_fig021448×581px
CH372C (SSOP-20) — 8.5. 单片机接口程序
8.5. 单片机接口程序
P13 · p13_fig01P13
CH372C (SSOP-20) — Datasheet Page 13 (p13_fig01)
Datasheet Page 13 (p13_fig01)

Technical Specifications & Part Details (CH372C)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH372C (SSOP-20) is a 20-pin standard electronic & interconnect component featuring a 7.20 × 5.30 × 1.85 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 3.3V to 5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.3V to 5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.20 × 5.30 × 1.85 mm (A1=0.15 mm)
Package family: TSSOP (SSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SSOP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.20 × 5.30 mm
Height (A) & Pitch (e)IPC-7351B
A=1.85mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.60 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SSOP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH372C (SSOP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH372C (SSOP-20)?

Manufactured by WCH, the CH372C is housed in a SSOP-20 package with 20 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 3.3V to 5V. Key pins include: 1 (INT#: Multiplexed I/O & Peripheral Pin INT# (General)), 2 (WR#: Multiplexed I/O & Peripheral Pin WR# (General)), 3 (RD#: Multiplexed I/O & Peripheral Pin RD# (General)), 4 (A0: Multiplexed I/O & Peripheral Pin A0 (General)), 5 (V3: Regulated Power Output (V3 — 3.3V to 5V)), 6 (UD+: Multiplexed I/O & Peripheral Pin UD+ (USB)).

What are the IPC-7351B PCB Footprint dimensions for CH372C?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH372C (SSOP-20) has a nominal body envelope of 5.30 × 7.20 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH372C?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH372C (WCH, SSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & CH372 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1INT#Digital_IOSignal terminal INT# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: INT#. Supported peripheral buses: General.
2WR#Digital_IOSignal terminal WR# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: WR#. Supported peripheral buses: General.
3RD#Digital_IOSignal terminal RD# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RD#. Supported peripheral buses: General.
4A0Digital_IOSignal terminal A0 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
5V3Power_OutRegulated power output rail (V3) operating in the 3.3V to 5V domain (Max rating: 5.0V).
6UD+Digital_IOSignal terminal UD+ (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
7UD-Digital_IOSignal terminal UD- (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
8XIDigital_IO12 MHz crystal oscillator input (XI); requires a 22pF load capacitor to GND (internally clocked on CH340C).
9XODigital_IO12 MHz crystal oscillator inverted output (XO); connect to crystal terminal and 22pF load capacitor to GND.
10D0Digital_IOSignal terminal D0 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D0. Supported peripheral buses: General.
11D1Digital_IOSignal terminal D1 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D1. Supported peripheral buses: General.
12D2Digital_IOSignal terminal D2 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D2. Supported peripheral buses: General.
13D3Digital_IOSignal terminal D3 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D3. Supported peripheral buses: General.
14D4Digital_IOSignal terminal D4 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D4. Supported peripheral buses: General.
15D5Digital_IOSignal terminal D5 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D5. Supported peripheral buses: General.
16D6Digital_IOSignal terminal D6 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D6. Supported peripheral buses: General.
17D7Digital_IOSignal terminal D7 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D7. Supported peripheral buses: General.
18GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
19CS#Digital_IOSignal terminal CS# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: CS#. Supported peripheral buses: General.
20VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V to 5V domain (Max rating: 5.0V).
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