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STM32H725VGH6 (TFBGA-100(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32H725VGH6

STTFBGA-100(8x8) · 100 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32H725VGH6 (TFBGA-100(8x8))A1PE6A2PE5A3PE2A4PB8A5BOOT0A6PB5A7PD6A8PD3A9PD2A10PC12B1PC14 - OSC32B2PC15 - OSC32B3PE3B4PE0B5PB7B6PB3(JTDO/ TRB7PD4B8PG11B9PC11B10PC10C1VSSC2VBATC3PE4C4PE1C5PB4 (NJTRST)C6PD7C7PD0C8PA15(JTDI)C9PA14 (JTCK/SC10PA13 (JTMS/ D1VSSSMPSD2VLXSMPSD3PDR_OND4PB6D5VSSD6VDDD7PG13D8VCAPD9PA12D10PA11E1VDDSMPSE2VFBSMPSE3PB9E4PF1E5VDDE6VDDLDOE7VSSE8PG12E9PA9E10PA10K10PB15K9PB14K8PB12K7PB10K6PE9K5PB1K4PB0K3PA7K2PA5K1PA4J10PD10J9PD8J8PB13J7PB11J6PE8J5PB2J4PC5J3PA6J2PA1J1VREF+H10PG3H9PG2H8PD9H7PD11H6PE10H5PE7H4PC4H3PA2H2VSSAH1VDDAG10PC8G9PC7G8PD15G7PD14G6VCAPG5PA3G4PF6G3PA0G2PH1 - OSC_OUG1PH0 - OSC_INF10PA8F9PC9F8PC6F7VDDLDOF6VDDF5VSSF4PF2F3PC0F2NRSTF1PC1Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1A2B2C2D2E2F2G2H2J2K2A3B3C3D3E3F3G3H3J3K3A4B4C4D4E4F4G4H4J4K4A5B5C5D5E5F5G5H5J5K5A6B6C6D6E6F6G6H6J6K6A7B7C7D7E7F7G7H7J7K7A8B8C8D8E8F8G8H8J8K8A9B9C9D9E9F9G9H9J9K9A10B10C10D10E10F10G10H10J10K10E=8.00mm · Pitch e=0.80mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PE6I/OMultiplexed I/O & Peripheral Pin PE6 (SPI, I2C)
A2PE5I/OMultiplexed I/O & Peripheral Pin PE5 (SPI)
A3PE2I/OMultiplexed I/O & Peripheral Pin PE2 (UART, SPI)
A4PB8I/OMultiplexed I/O & Peripheral Pin PB8 (UART, I2C, PWM)
A5BOOT0IInput-Only Pin BOOT0 (General)
A6PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C, PWM)
A7PD6I/OMultiplexed I/O & Peripheral Pin PD6 (UART, SPI, I2C)
A8PD3I/OMultiplexed I/O & Peripheral Pin PD3 (UART, SPI)
A9PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
A10PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI, I2C)
B1PC14 - OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK)
B2PC15 - OSC32_ OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_ OUT (RTC/CLK)
B3PE3I/OMultiplexed I/O & Peripheral Pin PE3 (UART)
B4PE0I/OMultiplexed I/O & Peripheral Pin PE0 (UART)
B5PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C, PWM)
B6PB3(JTDO/ TRACES WO)I/OMultiplexed I/O & Peripheral Pin PB3(JTDO/ TRACES WO) (UART, SPI, PWM, SWD/JTAG)
B7PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART)
B8PG11I/OMultiplexed I/O & Peripheral Pin PG11 (UART, SPI)
B9PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI, I2C)
B10PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI, I2C)
C1VSSGNDGround Reference Pin (VSS)
C2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
C3PE4I/OMultiplexed I/O & Peripheral Pin PE4 (SPI)
C4PE1I/OMultiplexed I/O & Peripheral Pin PE1 (UART)
C5PB4 (NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4 (NJTRST) (UART, SPI, PWM, SWD/JTAG)
C6PD7I/OMultiplexed I/O & Peripheral Pin PD7 (UART, SPI)
C7PD0I/OMultiplexed I/O & Peripheral Pin PD0 (UART)
C8PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG)
C9PA14 (JTCK/SWC LK)I/OMultiplexed I/O & Peripheral Pin PA14 (JTCK/SWC LK) (SWD/JTAG)
C10PA13 (JTMS/ SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13 (JTMS/ SWDIO) (SWD/JTAG)
D1VSSSMPSGNDGround Reference Pin (VSSSMPS)
D2VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
D3PDR_ONI/OMultiplexed I/O & Peripheral Pin PDR_ON (General)
D4PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C, PWM)
D5VSSGNDGround Reference Pin (VSS)
D6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D7PG13I/OMultiplexed I/O & Peripheral Pin PG13 (UART, SPI)
D8VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
D9PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART, SPI)
D10PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, SPI, PWM)
E1VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
E2VFBSMPSI/OMultiplexed I/O & Peripheral Pin VFBSMPS (General)
E3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (UART, SPI, I2C, PWM)
E4PF1I/OMultiplexed I/O & Peripheral Pin PF1 (I2C)
E5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E6VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
E7VSSGNDGround Reference Pin (VSS)
E8PG12I/OMultiplexed I/O & Peripheral Pin PG12 (UART, SPI)
E9PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, SPI, I2C, PWM)
E10PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, PWM)
F1PC1I/OMultiplexed I/O & Peripheral Pin PC1 (SPI, I2C, ADC, RTC/CLK)
F2NRSTISystem Enable & Hardware Reset (NRST)
F3PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
F4PF2I/OMultiplexed I/O & Peripheral Pin PF2 (I2C)
F5VSSGNDGround Reference Pin (VSS)
F6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F7VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
F8PC6I/OMultiplexed I/O & Peripheral Pin PC6 (UART, PWM)
F9PC9I/OMultiplexed I/O & Peripheral Pin PC9 (UART, I2C, PWM, RTC/CLK)
F10PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, I2C, RTC/CLK)
G1PH0 - OSC_INI/OMultiplexed I/O & Peripheral Pin PH0 - OSC_IN (RTC/CLK)
G2PH1 - OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1 - OSC_OUT (RTC/CLK)
G3PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM)
G4PF6I/OMultiplexed I/O & Peripheral Pin PF6 (UART, SPI, ADC)
G5PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
G6VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
G7PD14I/OMultiplexed I/O & Peripheral Pin PD14 (UART, PWM)
G8PD15I/OMultiplexed I/O & Peripheral Pin PD15 (UART, PWM)
G9PC7I/OMultiplexed I/O & Peripheral Pin PC7 (UART, PWM)
G10PC8I/OMultiplexed I/O & Peripheral Pin PC8 (UART, PWM)
H1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
H2VSSAGNDGround Reference Pin (VSSA)
H3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, SPI, ADC, PWM)
H4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
H5PE7I/OMultiplexed I/O & Peripheral Pin PE7 (UART)
H6PE10I/OMultiplexed I/O & Peripheral Pin PE10 (UART, PWM)
H7PD11I/OMultiplexed I/O & Peripheral Pin PD11 (UART, SPI, I2C)
H8PD9I/OMultiplexed I/O & Peripheral Pin PD9 (UART)
H9PG2I/OMultiplexed I/O & Peripheral Pin PG2 (General)
H10PG3I/OMultiplexed I/O & Peripheral Pin PG3 (General)
J1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
J2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
J3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
J4PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
J5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (SPI, I2C, RTC/CLK)
J6PE8I/OMultiplexed I/O & Peripheral Pin PE8 (UART, PWM)
J7PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C, PWM)
J8PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
J9PD8I/OMultiplexed I/O & Peripheral Pin PD8 (UART)
J10PD10I/OMultiplexed I/O & Peripheral Pin PD10 (UART)
K1PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
K2PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
K3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
K4PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, ADC, PWM)
K5PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
K6PE9I/OMultiplexed I/O & Peripheral Pin PE9 (UART, PWM)
K7PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, SPI, I2C, PWM)
K8PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
K9PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
K10PB15I/OMultiplexed I/O & Peripheral Pin PB15 (UART, SPI, PWM, RTC/CLK)
PIN A1 PE6
I/O
Multiplexed I/O & Peripheral Pin PE6 (SPI, I2C)
Design note: Alt: TRACED3 , TIM1_BKIN2SAI1D1 ,_ , TIM15_CH2 , SPI4_MOSI , SAI1_SDA_ , SAI4 SD_ASAI4D1_ ,_ , SAI4_MCLKB_ , TIM1_BKIN2COMP12_ , FMC_A22 , DCMI D7/PSSI_D7_ , LCD_G1EVENTOUT ,
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 23 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32H725VGH6 (ST · TFBGA-100(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32H725VGH6 (TFBGA-100(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32H725VGH6 (TFBGA-100(8x8)) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32H725VGH6 (TFBGA-100(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32H725VGH6 (TFBGA-100(8x8)) - 4. Package Dimensions (D×E×A)
TFBGA-100(8x8) · 8.00×8.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32H725VGH6 (TFBGA-100(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32H725VGH6 (TFBGA-100(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (23 figures · Page 1/2)
Showing 1–12 of 23 uncropped original figures for STM32H725
P56 · p56_fig01EXACT PACKAGE
STM32H725VGH6 (TFBGA-100(8x8)) — Figure 4. VFQFPN68 pinout
Figure 4. VFQFPN68 pinout
P56 · p56_fig02EXACT PACKAGE
STM32H725VGH6 (TFBGA-100(8x8)) — Figure 5. TFBGA100 pinout
Figure 5. TFBGA100 pinout
P1 · p01_fig01881×1115px
STM32H725VGH6 (TFBGA-100(8x8)) — • POR, PDR, PVD and BOR
• POR, PDR, PVD and BOR
P57 · p57_fig011553×1548px
STM32H725VGH6 (TFBGA-100(8x8)) — Figure 6. LQFP100 pinout
Figure 6. LQFP100 pinout
P59 · p59_fig011751×1679px
STM32H725VGH6 (TFBGA-100(8x8)) — Figure 8. LQFP144 pinout
Figure 8. LQFP144 pinout
P113 · p113_fig011546×2148px
STM32H725VGH6 (TFBGA-100(8x8)) — Figure 14. Power supply scheme
Figure 14. Power supply scheme
P147 · p147_fig011546×500px
STM32H725VGH6 (TFBGA-100(8x8)) — Figure 24. Typical application with an 8 MHz crystal
Figure 24. Typical application with an 8 MHz crystal
P148 · p148_fig011546×516px
STM32H725VGH6 (TFBGA-100(8x8)) — Figure 25. Typical application with a 32.768 kHz crystal
Figure 25. Typical application with a 32.768 kHz crystal
P267 · p267_fig011546×1369px
STM32H725VGH6 (TFBGA-100(8x8)) — Figure 84. UFBGA - 144 balls, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
Figure 84. UFBGA - 144 balls, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
P58 · p58_fig01EXACT PACKAGE
STM32H725VGH6 (TFBGA-100(8x8)) — Figure 6. LQFP100 pinout [LQFP-100(14x14)]
Figure 6. LQFP100 pinout [LQFP-100(14x14)]
P247 · p247_fig01EXACT PACKAGE
STM32H725VGH6 (TFBGA-100(8x8)) — Figure 77. LQFP100 package outline [LQFP-100(14x14)]
Figure 77. LQFP100 package outline [LQFP-100(14x14)]
P248 · p248_fig01EXACT PACKAGE
STM32H725VGH6 (TFBGA-100(8x8)) — Figure 78. LQFP100 package recommended footprint [LQFP-100(14x14)]
Figure 78. LQFP100 package recommended footprint [LQFP-100(14x14)]
Page 1 / 2 (23 extracted figures)

Technical Specifications & Part Details (STM32H725VGH6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32H725VGH6 (TFBGA-100(8x8)) is a 100-pin embedded microcontroller unit (mcu) featuring a 8.00 × 8.00 × 1.12 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.62 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, DAC, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.62 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
550 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
69 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 1.12 mm (A1=0.25 mm)
Package family: BGA (TFBGA-100(8x8))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, DAC, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32H725 (10)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (TFBGA-100(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.12mm · e=0.80mm
Pad Size (W × L)Level B
0.32 × 0.32 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TFBGA-100(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32H725VGH6 (TFBGA-100(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32H725VGH6 (TFBGA-100(8x8))?

Manufactured by ST, the STM32H725VGH6 is housed in a TFBGA-100(8x8) package with 100 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 1.62 V to 3.6 V. Key pins include: A1 (PE6: Multiplexed I/O & Peripheral Pin PE6 (SPI, I2C)), A2 (PE5: Multiplexed I/O & Peripheral Pin PE5 (SPI)), A3 (PE2: Multiplexed I/O & Peripheral Pin PE2 (UART, SPI)), A4 (PB8: Multiplexed I/O & Peripheral Pin PB8 (UART, I2C, PWM)), A5 (BOOT0: Input-Only Pin BOOT0 (General)), A6 (PB5: Multiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C, PWM)).

What are the IPC-7351B PCB Footprint dimensions for STM32H725VGH6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H725VGH6 (TFBGA-100(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.80 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H725VGH6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H725VGH6 (ST, TFBGA-100(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32H725 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MOSI. Supported peripheral buses: SPI, I2C.
A2PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MISO. Supported peripheral buses: SPI.
A3PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_SCK. Supported peripheral buses: UART, SPI.
A4PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: UART, I2C, PWM.
A5BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A6PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSI, I2C4_SMBA, SPI3_MOSI, SPI6_MOSI. Supported peripheral buses: UART, SPI, I2C, PWM.
A7PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI, I2C.
A8PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI.
A9PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
A10PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C5_SMBA, SPI6_SCK, SPI3_MOSI. Supported peripheral buses: UART, SPI, I2C.
B1PC14 - OSC32_INDigital_IOSignal terminal PC14 - OSC32_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN. Supported peripheral buses: RTC/CLK.
B2PC15 - OSC32_ OUTDigital_IOSignal terminal PC15 - OSC32_ OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15 - OSC32_ OUT. Supported peripheral buses: RTC/CLK.
B3PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: UART.
B4PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: UART.
B5PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SDA. Supported peripheral buses: UART, I2C, PWM.
B6PB3(JTDO/ TRACES WO)Digital_IOSignal terminal PB3(JTDO/ TRACES WO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK, SPI3_SCK, SPI6_SCK. Supported peripheral buses: UART, SPI, PWM, SWD/JTAG.
B7PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: UART.
B8PG11Digital_IOSignal terminal PG11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI.
B9PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C5_SCL, SPI3_MISO. Supported peripheral buses: UART, SPI, I2C.
B10PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C5_SDA, SPI3_SCK. Supported peripheral buses: UART, SPI, I2C.
C1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C3PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSS. Supported peripheral buses: SPI.
C4PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: UART.
C5PB4 (NJTRST)Digital_IOSignal terminal PB4 (NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, SPI3_MISO, SPI2_NSS, SPI6_MISO. Supported peripheral buses: UART, SPI, PWM, SWD/JTAG.
C6PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI.
C7PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: UART.
C8PA15(JTDI)Digital_IOSignal terminal PA15(JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS, SPI6_NSS. Supported peripheral buses: UART, SPI, SWD/JTAG.
C9PA14 (JTCK/SWC LK)Digital_IOSignal terminal PA14 (JTCK/SWC LK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (JTCK/SWC LK). Supported peripheral buses: SWD/JTAG.
C10PA13 (JTMS/ SWDIO)Digital_IOSignal terminal PA13 (JTMS/ SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMS/ SWDIO). Supported peripheral buses: SWD/JTAG.
D1VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
D2VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
D3PDR_ONDigital_IOSignal terminal PDR_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General.
D4PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL, I2C4_SCL. Supported peripheral buses: UART, I2C, PWM.
D5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D6VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D7PG13Digital_IOSignal terminal PG13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI6_SCK. Supported peripheral buses: UART, SPI.
D8VCAPDigital_IOSignal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
D9PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI.
D10PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI, PWM.
E1VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E2VFBSMPSDigital_IOSignal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General.
E3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA, SPI2_NSS, I2C4_SDA, I2C4_SMBA. Supported peripheral buses: UART, SPI, I2C, PWM.
E4PF1Digital_IOSignal terminal PF1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL, I2C5_SCL. Supported peripheral buses: I2C.
E5VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E6VDDLDOPower_InPrimary positive power supply input (VDDLDO) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E8PG12Digital_IOSignal terminal PG12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI6_MISO. Supported peripheral buses: UART, SPI.
E9PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SMBA, SPI2_SCK, I2C5_SMBA. Supported peripheral buses: UART, SPI, I2C, PWM.
E10PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART, PWM.
F1PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, I2C, ADC, RTC/CLK.
F2NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
F3PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
F4PF2Digital_IOSignal terminal PF2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SMBA, I2C5_SMBA. Supported peripheral buses: I2C.
F5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F6VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F7VDDLDOPower_InPrimary positive power supply input (VDDLDO) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F8PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: UART, PWM.
F9PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA. Supported peripheral buses: UART, I2C, PWM, RTC/CLK.
F10PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL, I2C5_SCL. Supported peripheral buses: UART, I2C, RTC/CLK.
G1PH0 - OSC_INDigital_IOSignal terminal PH0 - OSC_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC_IN. Supported peripheral buses: RTC/CLK.
G2PH1 - OSC_OUTDigital_IOSignal terminal PH1 - OSC_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC_OUT. Supported peripheral buses: RTC/CLK.
G3PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI6_NSS. Supported peripheral buses: UART, SPI, ADC, PWM.
G4PF6Digital_IOSignal terminal PF6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI5_NSS. Supported peripheral buses: UART, SPI, ADC.
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