Mechanical Dimensions & Land Pattern (UFBGA-201)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.50mm · e=0.65mm
Pad Size (W × L)Level B
0.30 × 0.30 mm
Pins / Total PadsTopology
201P / 201Pad (BGA_GRID)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit UFBGA-201 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32H725IGK6 (UFBGA-201)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32H725IGK6 (UFBGA-201)?
Manufactured by ST, the STM32H725IGK6 is housed in a UFBGA-201 package with 201 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 1.62 V to 3.6 V. Key pins include: A1 (VSS: Ground Reference Pin (VSS)), A2 (PB8: Multiplexed I/O & Peripheral Pin PB8 (General)), A3 (VDDLDO: Power Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))), A4 (VCAP: Multiplexed I/O & Peripheral Pin VCAP (General)), A5 (PB6: Multiplexed I/O & Peripheral Pin PB6 (General)), A6 (PB3: Multiplexed I/O & Peripheral Pin PB3 (General)).
What are the IPC-7351B PCB Footprint dimensions for STM32H725IGK6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H725IGK6 (UFBGA-201) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.65 mm, and 201 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H725IGK6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H725IGK6 (ST, UFBGA-201) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (201 pins) & STM32H725 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| A1 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| A2 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General. |
| A3 | VDDLDO | Power_In | Primary positive power supply input (VDDLDO) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| A4 | VCAP | Digital_IO | Signal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General. |
| A5 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General. |
| A6 | PB3 | Digital_IO | Signal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General. |
| A7 | PG11 | Digital_IO | Signal terminal PG11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG11. Supported peripheral buses: General. |
| A8 | PG9 | Digital_IO | Signal terminal PG9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG9. Supported peripheral buses: General. |
| A9 | PD3 | Digital_IO | Signal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General. |
| A10 | PD1 | Digital_IO | Signal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General. |
| A11 | PA15 | Digital_IO | Signal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General. |
| A12 | PA14 | Digital_IO | Signal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General. |
| A13 | VDDLDO | Power_In | Primary positive power supply input (VDDLDO) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| A14 | VCAP | Digital_IO | Signal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General. |
| A15 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| B1 | PE4 | Digital_IO | Signal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General. |
| B2 | PE3 | Digital_IO | Signal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General. |
| B3 | PB9 | Digital_IO | Signal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General. |
| B4 | PE0 | Digital_IO | Signal terminal PE0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General. |
| B5 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General. |
| B6 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General. |
| B7 | PG13 | Digital_IO | Signal terminal PG13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG13. Supported peripheral buses: General. |
| B8 | PD7 | Digital_IO | Signal terminal PD7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General. |
| B9 | PD5 | Digital_IO | Signal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General. |
| B10 | PD2 | Digital_IO | Signal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General. |
| B11 | PC12 | Digital_IO | Signal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General. |
| B12 | PH14 | Digital_IO | Signal terminal PH14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH14. Supported peripheral buses: General. |
| B13 | PA13 | Digital_IO | Signal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General. |
| B14 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General. |
| B15 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General. |
| C1 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General. |
| C2 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| C3 | PE2 | Digital_IO | Signal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General. |
| C4 | PE1 | Digital_IO | Signal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General. |
| C5 | BOOT0 | Digital_IO | Signal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General. |
| C6 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General. |
| C7 | PG14 | Digital_IO | Signal terminal PG14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG14. Supported peripheral buses: General. |
| C8 | PG10 | Digital_IO | Signal terminal PG10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG10. Supported peripheral buses: General. |
| C9 | PD4 | Digital_IO | Signal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General. |
| C10 | PD0 | Digital_IO | Signal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General. |
| C11 | PC11 | Digital_IO | Signal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General. |
| C12 | PC10 | Digital_IO | Signal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General. |
| C13 | PH13 | Digital_IO | Signal terminal PH13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH13. Supported peripheral buses: General. |
| C14 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General. |
| C15 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General. |
| D1 | PC15-OSC32_OUT | Digital_IO | Signal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK. |
| D2 | PC14-OSC32_IN | Digital_IO | Signal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK. |
| D3 | PE5 | Digital_IO | Signal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General. |
| D4 | PDR_ON | Digital_IO | Signal terminal PDR_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General. |
| D5 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| D6 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| D7 | PG15 | Digital_IO | Signal terminal PG15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG15. Supported peripheral buses: General. |
| D8 | PG12 | Digital_IO | Signal terminal PG12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG12. Supported peripheral buses: General. |
| D9 | PD6 | Digital_IO | Signal terminal PD6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General. |
| D10 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| D11 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| D12 | PH15 | Digital_IO | Signal terminal PH15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH15. Supported peripheral buses: General. |
| D13 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General. |
| D14 | PC8 | Digital_IO | Signal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General. |
| D15 | PC7 | Digital_IO | Signal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General. |
| E1 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| E2 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| E3 | PE6 | Digital_IO | Signal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General. |
| E4 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |