![STM32WB15CCY6TR (WLCSP-49) — Figure 8. STM32WB15CCU UFQFPN48 pinout (1) (2) [UFQFPN-48(7x7)]](/api/v1/assets/C3606695/extracted/figures/p46_fig01.png)
![STM32WB15CCY6TR (WLCSP-49) — Figure 9. STM32WB15CCU UFQFPN48E pinout (1) (2) [UFQFPN-48(7x7)]](/api/v1/assets/C3606695/extracted/figures/p46_fig02.png)
![STM32WB15CCY6TR (WLCSP-49) — Figure 27. UFQFPN48 outline [UFQFPN-48(7x7)]](/api/v1/assets/C3606695/extracted/figures/p116_fig01.png)
![STM32WB15CCY6TR (WLCSP-49) — Figure 28. UFQFPN48 recommended footprint [UFQFPN-48(7x7)]](/api/v1/assets/C3606695/extracted/figures/p117_fig01.png)
![STM32WB15CCY6TR (WLCSP-49) — • Energy benckmark - 318 ULPMark™ CP score [UFQFPN-48(7x7)]](/api/v1/assets/C3606695/extracted/figures/p01_fig01.png)
![STM32WB15CCY6TR (WLCSP-49) — Pinouts and pin description STM32WB15CC [UFQFPN-48(7x7)]](/api/v1/assets/C3606695/extracted/figures/p52_fig01.png)
![STM32WB15CCY6TR (WLCSP-49) — Figure 31. WLCSP49 recommended footprint [UFQFPN-48(7x7)]](/api/v1/assets/C3606695/extracted/figures/p121_fig01.png)
![STM32WB15CCY6TR (WLCSP-49) — STM32WB15CC Revision history [UFQFPN-48(7x7)]](/api/v1/assets/C3606695/extracted/figures/p129_fig01.png)
UFQFPN-48(7x7) · 49P
Synchronized Pinout (Symbol / 2D / 3D) (49/49)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| A1 | VDDSMPS | Power | Power Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V)) |
| A2 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (General) |
| A3 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (General) |
| A4 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| A5 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (General) |
| A6 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (General) |
| A7 | PC14-OSC32_IN | I/O | Multiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK) |
| B1 | VLXSMPS | I/O | Multiplexed I/O & Peripheral Pin VLXSMPS (General) |
| B2 | PA13 | I/O | Multiplexed I/O & Peripheral Pin PA13 (General) |
| B3 | PA14 | I/O | Multiplexed I/O & Peripheral Pin PA14 (General) |
| B4 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (General) |
| B5 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (General) |
| B6 | PH3-BOOT0 | I/O | Multiplexed I/O & Peripheral Pin PH3-BOOT0 (General) |
| B7 | PC15-OSC32_OUT | I/O | Multiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK) |
| C1 | VSSSMPS | GND | Ground Reference Pin (VSSSMPS) |
| C2 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (General) |
| C3 | VSS | GND | Ground Reference Pin (VSS) |
| C4 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (General) |
| C5 | VBAT | Power | Power Supply Input (VBAT — 3.3V VDD (Max 4.0V)) |
| C6 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (General) |
| C7 | PB11/NRST | I/O | Multiplexed I/O & Peripheral Pin PB11/NRST (General) |
| D1 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| D2 | VFBSMPS | I/O | Multiplexed I/O & Peripheral Pin VFBSMPS (General) |
| D3 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (General) |
| D4 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (General) |
| D5 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (General) |
| D6 | VSS | GND | Ground Reference Pin (VSS) |
| D7 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| E1 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (General) |
| E2 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (General) |
| E3 | AT0 | I/O | Multiplexed I/O & Peripheral Pin AT0 (General) |
| E4 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (General) |
| E5 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (General) |
| E6 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (General) |
| E7 | VDDA | Power | Power Supply Input (VDDA — 3.3V VDD (Max 4.0V)) |
| F1 | OSC_IN | I/O | Multiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK) |
| F2 | OSC_OUT | I/O | Multiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK) |
| F3 | AT1 | I/O | Multiplexed I/O & Peripheral Pin AT1 (General) |
| F4 | VSS | GND | Ground Reference Pin (VSS) |
| F5 | VSS | GND | Ground Reference Pin (VSS) |
| F6 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (General) |
| F7 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (General) |
| G1 | VSSRF | GND | Ground Reference Pin (VSSRF) |
| G2 | VDDRF | Power | Power Supply Input (VDDRF — 3.3V VDD (Max 4.0V)) |
| G3 | VSSRF | GND | Ground Reference Pin (VSSRF) |
| G4 | RF1 | I/O | Multiplexed I/O & Peripheral Pin RF1 (General) |
| G5 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| G6 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (General) |
| G7 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (General) |
PIN A1 VDDSMPS
PowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
WLCSP-49 · 3.30×3.30mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for STM32WB15
P46 · p46_fig01EXACT PACKAGE
P46 · p46_fig02EXACT PACKAGE
P116 · p116_fig01EXACT PACKAGE
P117 · p117_fig01EXACT PACKAGE
P1 · p01_fig011072×611px
P52 · p52_fig011741×636px
P121 · p121_fig011548×1259px
P129 · p129_fig011548×1476px
Technical Specifications & Part Details (STM32WB15CCY6TR)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32WB15CCY6TR (WLCSP-49) is a 49-pin embedded microcontroller unit (mcu) featuring a 3.30 × 3.30 × 0.55 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.30 × 3.30 × 0.55 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-49)
Pin Count & Lead PitchN / e
49 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol49 auto-grouped pins
IPC-7351B Land Pattern49 pads · Pitch 0.40mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32WB15 (2)
WLCSP-49 · 49P
Mechanical Dimensions & Land Pattern (WLCSP-49)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
3.30 × 3.30 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.40mm
Pad Size (W × L)Level B
0.21 × 0.21 mm
Pins / Total PadsTopology
49P / 49Pad (BGA_GRID)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit WLCSP-49 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32WB15CCY6TR (WLCSP-49)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32WB15CCY6TR (WLCSP-49)?
Manufactured by ST, the STM32WB15CCY6TR is housed in a WLCSP-49 package with 49 pins and a 0.40 mm lead pitch. Key pins include: A1 (VDDSMPS: Power Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))), A2 (PA11: Multiplexed I/O & Peripheral Pin PA11 (General)), A3 (PA12: Multiplexed I/O & Peripheral Pin PA12 (General)), A4 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), A5 (PB5: Multiplexed I/O & Peripheral Pin PB5 (General)), A6 (PB7: Multiplexed I/O & Peripheral Pin PB7 (General)).
What are the IPC-7351B PCB Footprint dimensions for STM32WB15CCY6TR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WB15CCY6TR (WLCSP-49) has a nominal body envelope of 3.30 × 3.30 mm, pitch e = 0.40 mm, and 49 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WB15CCY6TR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WB15CCY6TR (ST, WLCSP-49) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (49 pins) & STM32WB15 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| A1 | VDDSMPS | Power_In | Primary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| A2 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General. |
| A3 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General. |
| A4 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| A5 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General. |
| A6 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General. |
| A7 | PC14-OSC32_IN | Digital_IO | Signal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK. |
| B1 | VLXSMPS | Digital_IO | Signal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General. |
| B2 | PA13 | Digital_IO | Signal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General. |
| B3 | PA14 | Digital_IO | Signal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General. |
| B4 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General. |
| B5 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General. |
| B6 | PH3-BOOT0 | Digital_IO | Signal terminal PH3-BOOT0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH3-BOOT0. Supported peripheral buses: General. |
| B7 | PC15-OSC32_OUT | Digital_IO | Signal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK. |
| C1 | VSSSMPS | GND | 0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks. |
| C2 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General. |
| C3 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| C4 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General. |
| C5 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| C6 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General. |
| C7 | PB11/NRST | Digital_IO | Signal terminal PB11/NRST (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB11/NRST. Supported peripheral buses: General. |
| D1 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| D2 | VFBSMPS | Digital_IO | Signal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General. |
| D3 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General. |
| D4 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General. |
| D5 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General. |
| D6 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| D7 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| E1 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General. |
| E2 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General. |
| E3 | AT0 | Digital_IO | Signal terminal AT0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: AT0. Supported peripheral buses: General. |
| E4 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General. |
| E5 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General. |
| E6 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General. |
| E7 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| F1 | OSC_IN | Digital_IO | Signal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK. |
| F2 | OSC_OUT | Digital_IO | Signal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK. |
| F3 | AT1 | Digital_IO | Signal terminal AT1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: AT1. Supported peripheral buses: General. |
| F4 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| F5 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| F6 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General. |
| F7 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General. |
| G1 | VSSRF | GND | 0V electrical ground return terminal (VSSRF) for internal core logic, I/O drivers, and analog sub-blocks. |
| G2 | VDDRF | Power_In | Primary positive power supply input (VDDRF) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| G3 | VSSRF | GND | 0V electrical ground return terminal (VSSRF) for internal core logic, I/O drivers, and analog sub-blocks. |
| G4 | RF1 | Digital_IO | Signal terminal RF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RF1. Supported peripheral buses: General. |
| G5 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| G6 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General. |
| G7 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General. |