Mechanical Dimensions & Land Pattern (DFN-10-EP(2x2))
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit DFN-10-EP(2x2) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH224Q (DFN-10-EP(2x2))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH224Q (DFN-10-EP(2x2))?
Manufactured by WCH, the CH224Q is housed in a DFN-10-EP(2x2) package with 11 pins and a 0.40 mm lead pitch. Key pins include: 1 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 2 (GND: Ground Reference Pin (GND)), 3 (PG: Multiplexed I/O & Peripheral Pin PG (General)), 4 (DP: Multiplexed I/O & Peripheral Pin DP (General)), 5 (DM: Multiplexed I/O & Peripheral Pin DM (General)), 6 (CFG: Multiplexed I/O & Peripheral Pin CFG (General)).
What are the IPC-7351B PCB Footprint dimensions for CH224Q?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH224Q (DFN-10-EP(2x2)) has a nominal body envelope of 2.00 × 2.00 mm, pitch e = 0.40 mm, and 11 copper pads plus a central exposed thermal pad (EPAD) of 1.40 × 0.90 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH224Q?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH224Q (WCH, DFN-10-EP(2x2)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (11 pins) & CH221 / CH224 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 2 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 3 | PG | Digital_IO | Signal terminal PG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG. Supported peripheral buses: General. |
| 4 | DP | Digital_IO | Signal terminal DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP. Supported peripheral buses: General. |
| 5 | DM | Digital_IO | Signal terminal DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DM. Supported peripheral buses: General. |
| 6 | CFG | Digital_IO | Signal terminal CFG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG. Supported peripheral buses: General. |
| 7 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 8 | IO0 | Digital_IO | GPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin) |
| 9 | CFG1 I | Digital_IO | Signal terminal CFG1 I (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG1 I. Supported peripheral buses: General. |
| 10 | IO5 | Digital_IO | GPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4 |
| 11 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |