Mechanical Dimensions & Land Pattern (ESSOP-10)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit ESSOP-10 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH224A (ESSOP-10)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH224A (ESSOP-10)?
Manufactured by WCH, the CH224A is housed in a ESSOP-10 package with 11 pins and a 1.00 mm lead pitch, supporting a VCC supply range of 4V to 30V. Key pins include: 1 (VDD P: Power Supply Input (VDD P — 4V to 30V)), 2 (CFG2 I: Multiplexed I/O & Peripheral Pin CFG2 I (General)), 3 (CFG3 I: Multiplexed I/O & Peripheral Pin CFG3 I (General)), 4 (DP: Multiplexed I/O & Peripheral Pin DP (General)), 5 (DM: Multiplexed I/O & Peripheral Pin DM (General)), 6 (I/O CC2: Multiplexed I/O & Peripheral Pin I/O CC2 (General)).
What are the IPC-7351B PCB Footprint dimensions for CH224A?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH224A (ESSOP-10) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.00 mm, and 11 copper pads plus a central exposed thermal pad (EPAD) of 2.30 × 3.00 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH224A?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH224A (WCH, ESSOP-10) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (11 pins) & CH221 / CH224 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VDD P | Power_In | Primary positive power supply input (VDD P) operating in the 4V to 30V domain (Max rating: 30.0V). |
| 2 | CFG2 I | Digital_IO | Signal terminal CFG2 I (I/O, 4V to 30V domain). Multiplexed alternate functions: CFG2 I. Supported peripheral buses: General. |
| 3 | CFG3 I | Digital_IO | Signal terminal CFG3 I (I/O, 4V to 30V domain). Multiplexed alternate functions: CFG3 I. Supported peripheral buses: General. |
| 4 | DP | Digital_IO | Signal terminal DP (I/O, 4V to 30V domain). Multiplexed alternate functions: DP. Supported peripheral buses: General. |
| 5 | DM | Digital_IO | Signal terminal DM (I/O, 4V to 30V domain). Multiplexed alternate functions: DM. Supported peripheral buses: General. |
| 6 | I/O CC2 | Digital_IO | Signal terminal I/O CC2 (I/O, 4V to 30V domain). Multiplexed alternate functions: I/O CC2. Supported peripheral buses: General. |
| 7 | CC1 | Digital_IO | Signal terminal CC1 (I/O, 4V to 30V domain). Multiplexed alternate functions: CC1. Supported peripheral buses: General. |
| 8 | VBUS I | Power_In | Primary positive power supply input (VBUS I) operating in the 4V to 30V domain (Max rating: 30.0V). |
| 9 | CFG1 I | Digital_IO | Signal terminal CFG1 I (I/O, 4V to 30V domain). Multiplexed alternate functions: CFG1 I. Supported peripheral buses: General. |
| 10 | PG OD | Digital_IO | Signal terminal PG OD (I/O, 4V to 30V domain). Multiplexed alternate functions: PG OD. Supported peripheral buses: CAN. |
| 11 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |