STM32F765ZIT7 (LQFP-144(20x20)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of STM32F765ZIT7 (LQFP-144(20x20))?

Manufactured by ST, the STM32F765ZIT7 is housed in a LQFP-144(20x20) package with 144 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), 2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), 3 (PE4: Multiplexed I/O & Peripheral Pin PE4 (SPI)), 4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (SPI)), 5 (PE6: Multiplexed I/O & Peripheral Pin PE6 (SPI)), 6 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))).

Q: What are the IPC-7351B PCB Footprint dimensions for STM32F765ZIT7?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F765ZIT7 (LQFP-144(20x20)) has a nominal body envelope of 20.00 × 20.00 mm, pitch e = 0.50 mm, and 144 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F765ZIT7?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F765ZIT7 (ST, LQFP-144(20x20)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 20.00mm × 20.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (144/144)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	PE2	I/O	Multiplexed I/O & Peripheral Pin PE2 (General)
2	PE3	I/O	Multiplexed I/O & Peripheral Pin PE3 (General)
3	PE4	I/O	Multiplexed I/O & Peripheral Pin PE4 (SPI)
4	PE5	I/O	Multiplexed I/O & Peripheral Pin PE5 (SPI)
5	PE6	I/O	Multiplexed I/O & Peripheral Pin PE6 (SPI)
6	VBAT	Power	Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))
7	PC13	I/O	Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
8	PC14- OSC32_IN	I/O	Multiplexed I/O & Peripheral Pin PC14- OSC32_IN (RTC/CLK)
9	PC15- OSC32_OUT	I/O	Multiplexed I/O & Peripheral Pin PC15- OSC32_OUT (RTC/CLK)
10	VSS	GND	Ground Reference Pin (VSS)
11	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
12	PH0- OSC_IN	I/O	Multiplexed I/O & Peripheral Pin PH0- OSC_IN (RTC/CLK)
13	PH1- OSC_OUT	I/O	Multiplexed I/O & Peripheral Pin PH1- OSC_OUT (RTC/CLK)
14	NRST	I	System Enable & Hardware Reset (NRST)
15	PC0	I/O	Multiplexed I/O & Peripheral Pin PC0 (ADC)
16	PC1	I/O	Multiplexed I/O & Peripheral Pin PC1 (SPI, I2C, ADC, RTC/CLK)
17	PC2	I/O	Multiplexed I/O & Peripheral Pin PC2 (SPI, ADC)
18	PC3	I/O	Multiplexed I/O & Peripheral Pin PC3 (ADC)
19	VSSA	GND	Ground Reference Pin (VSSA)
20	VREF+	Analog	Multiplexed I/O & Peripheral Pin VREF+ (General)
21	VDDA	Power	Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))
22	PA0- WKUP	I/O	Multiplexed I/O & Peripheral Pin PA0- WKUP (UART, ADC)
23	PA1	I/O	Multiplexed I/O & Peripheral Pin PA1 (UART, ADC)
24	PA2	I/O	Multiplexed I/O & Peripheral Pin PA2 (SPI, ADC)
25	PA3	I/O	Multiplexed I/O & Peripheral Pin PA3 (ADC)
26	VSS	GND	Ground Reference Pin (VSS)
27	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
28	PA4	I/O	Multiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
29	PA5	I/O	Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC)
30	PA6	I/O	Multiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
31	PA7	I/O	Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
32	PC4	I/O	Multiplexed I/O & Peripheral Pin PC4 (UART, ADC)
33	PC5	I/O	Multiplexed I/O & Peripheral Pin PC5 (UART, ADC)
34	PB0	I/O	Multiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
35	PB1	I/O	Multiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
36	PB2	I/O	Multiplexed I/O & Peripheral Pin PB2 (SPI, I2C)
37	PE7	I/O	Multiplexed I/O & Peripheral Pin PE7 (General)
38	PE8	I/O	Multiplexed I/O & Peripheral Pin PE8 (PWM)
39	PE9	I/O	Multiplexed I/O & Peripheral Pin PE9 (UART, PWM)
40	PE10	I/O	Multiplexed I/O & Peripheral Pin PE10 (PWM)
41	PE11	I/O	Multiplexed I/O & Peripheral Pin PE11 (SPI)
42	PE12	I/O	Multiplexed I/O & Peripheral Pin PE12 (SPI)
43	PE13	I/O	Multiplexed I/O & Peripheral Pin PE13 (SPI)
44	PE14	I/O	Multiplexed I/O & Peripheral Pin PE14 (SPI)
45	PE15	I/O	Multiplexed I/O & Peripheral Pin PE15 (General)
46	PB10	I/O	Multiplexed I/O & Peripheral Pin PB10 (UART, I2C)
47	PB11	I/O	Multiplexed I/O & Peripheral Pin PB11 (UART, I2C)
48	VCAP_1	I/O	Multiplexed I/O & Peripheral Pin VCAP_1 (General)
49	VSS	GND	Exposed Thermal & Ground Pad (VSS)
50	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
51	PB12	I/O	Multiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
52	PB13	I/O	Multiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
53	PB14	I/O	Multiplexed I/O & Peripheral Pin PB14 (UART, SPI)
54	PB15	I/O	Multiplexed I/O & Peripheral Pin PB15 (UART, RTC/CLK)
55	PD8	I/O	Multiplexed I/O & Peripheral Pin PD8 (UART)
56	PD9	I/O	Multiplexed I/O & Peripheral Pin PD9 (General)
57	PD10	I/O	Multiplexed I/O & Peripheral Pin PD10 (General)
58	PD11	I/O	Multiplexed I/O & Peripheral Pin PD11 (UART, I2C)
59	PD12	I/O	Multiplexed I/O & Peripheral Pin PD12 (General)
60	PD13	I/O	Multiplexed I/O & Peripheral Pin PD13 (I2C, PWM)
61	PD14	I/O	Multiplexed I/O & Peripheral Pin PD14 (UART)
62	PD15	I/O	Multiplexed I/O & Peripheral Pin PD15 (UART)
63	PC6	I/O	Multiplexed I/O & Peripheral Pin PC6 (PWM)
64	PC7	I/O	Multiplexed I/O & Peripheral Pin PC7 (PWM)
65	PC8	I/O	Multiplexed I/O & Peripheral Pin PC8 (UART)
66	PC9	I/O	Multiplexed I/O & Peripheral Pin PC9 (I2C, RTC/CLK)
67	PA8	I/O	Multiplexed I/O & Peripheral Pin PA8 (UART, CAN, RTC/CLK)
68	PA9	I/O	Multiplexed I/O & Peripheral Pin PA9 (UART, I2C)
69	PA10	I/O	Multiplexed I/O & Peripheral Pin PA10 (UART)
70	PA11	I/O	Multiplexed I/O & Peripheral Pin PA11 (UART, SPI, PWM)
71	PA12	I/O	Multiplexed I/O & Peripheral Pin PA12 (UART, SPI, CAN)
72	PA13(JTM S-SWDIO)	I/O	Multiplexed I/O & Peripheral Pin PA13(JTM S-SWDIO) (SWD/JTAG)
73	VCAP_2	I/O	Multiplexed I/O & Peripheral Pin VCAP_2 (General)
74	VSS	GND	Ground Reference Pin (VSS)
75	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
76	PA14(JTC K-SWCLK)	I/O	Multiplexed I/O & Peripheral Pin PA14(JTC K-SWCLK) (SWD/JTAG)
77	PA15(JTDI )	I/O	Multiplexed I/O & Peripheral Pin PA15(JTDI ) (UART, SPI, CAN, SWD/JTAG)
78	PC10	I/O	Multiplexed I/O & Peripheral Pin PC10 (UART, SPI)
79	PC11	I/O	Multiplexed I/O & Peripheral Pin PC11 (SPI)
80	PC12	I/O	Multiplexed I/O & Peripheral Pin PC12 (UART, SPI)
81	PD0	I/O	Multiplexed I/O & Peripheral Pin PD0 (UART)
82	PD1	I/O	Multiplexed I/O & Peripheral Pin PD1 (UART)
83	PD2	I/O	Multiplexed I/O & Peripheral Pin PD2 (UART)
84	PD3	I/O	Multiplexed I/O & Peripheral Pin PD3 (UART)
85	PD4	I/O	Multiplexed I/O & Peripheral Pin PD4 (General)
86	PD5	I/O	Multiplexed I/O & Peripheral Pin PD5 (UART)
87	PD6	I/O	Multiplexed I/O & Peripheral Pin PD6 (UART)
88	PD7	I/O	Multiplexed I/O & Peripheral Pin PD7 (UART)
89	PB3 (JTDO / TRACESW O)	I/O	Multiplexed I/O & Peripheral Pin PB3 (JTDO / TRACESW O) (UART, SPI, PWM, CAN, SWD/JTAG)
90	PB4(NJTR ST)	I/O	Multiplexed I/O & Peripheral Pin PB4(NJTR ST) (UART, SPI, SWD/JTAG)
91	PB5	I/O	Multiplexed I/O & Peripheral Pin PB5 (UART, SPI, CAN)
92	PB6	I/O	Multiplexed I/O & Peripheral Pin PB6 (UART, I2C)
93	PB7	I/O	Multiplexed I/O & Peripheral Pin PB7 (UART, I2C)
94	BOOT0	I	Input-Only Pin BOOT0 (General)
95	PB8	I/O	Multiplexed I/O & Peripheral Pin PB8 (UART, I2C, CAN)
96	PB9	I/O	Multiplexed I/O & Peripheral Pin PB9 (SPI, I2C, CAN)
97	PE0	I/O	Multiplexed I/O & Peripheral Pin PE0 (General)
98	PE1	I/O	Multiplexed I/O & Peripheral Pin PE1 (UART)
99	VSS	GND	Ground Reference Pin (VSS)
100	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
101	PA9	I/O	Multiplexed I/O & Peripheral Pin PA9 (General)
102	PA10	I/O	Multiplexed I/O & Peripheral Pin PA10 (General)
103	PA11	I/O	Multiplexed I/O & Peripheral Pin PA11 (General)
104	PA12	I/O	Multiplexed I/O & Peripheral Pin PA12 (General)
105	PA13	I/O	Multiplexed I/O & Peripheral Pin PA13 (General)
106	VCAP_2	I/O	Multiplexed I/O & Peripheral Pin VCAP_2 (General)
107	VSS	GND	Ground Reference Pin (VSS)
108	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
109	PA14	I/O	Multiplexed I/O & Peripheral Pin PA14 (General)
110	PA15	I/O	Multiplexed I/O & Peripheral Pin PA15 (General)
111	PC10	I/O	Multiplexed I/O & Peripheral Pin PC10 (General)
112	PC11	I/O	Multiplexed I/O & Peripheral Pin PC11 (General)
113	PC12	I/O	Multiplexed I/O & Peripheral Pin PC12 (General)
114	PD0	I/O	Multiplexed I/O & Peripheral Pin PD0 (General)
115	PD1	I/O	Multiplexed I/O & Peripheral Pin PD1 (General)
116	PD2	I/O	Multiplexed I/O & Peripheral Pin PD2 (General)
117	PD3	I/O	Multiplexed I/O & Peripheral Pin PD3 (General)
118	PD4	I/O	Multiplexed I/O & Peripheral Pin PD4 (General)
119	PD5	I/O	Multiplexed I/O & Peripheral Pin PD5 (General)
120	VSS	GND	Ground Reference Pin (VSS)
121	VDDSDMMC	Power	Power Supply Input (VDDSDMMC — 3.3V VDD (Max 4.0V))
122	PD6	I/O	Multiplexed I/O & Peripheral Pin PD6 (General)
123	PD7	I/O	Multiplexed I/O & Peripheral Pin PD7 (General)
124	PG9	I/O	Multiplexed I/O & Peripheral Pin PG9 (General)
125	PG10	I/O	Multiplexed I/O & Peripheral Pin PG10 (General)
126	PG11	I/O	Multiplexed I/O & Peripheral Pin PG11 (General)
127	PG12	I/O	Multiplexed I/O & Peripheral Pin PG12 (General)
128	PG13	I/O	Multiplexed I/O & Peripheral Pin PG13 (General)
129	PG14	I/O	Multiplexed I/O & Peripheral Pin PG14 (General)
130	VSS	GND	Ground Reference Pin (VSS)
131	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
132	PG15	I/O	Multiplexed I/O & Peripheral Pin PG15 (General)
133	PB3	I/O	Multiplexed I/O & Peripheral Pin PB3 (General)
134	PB4	I/O	Multiplexed I/O & Peripheral Pin PB4 (General)
135	PB5	I/O	Multiplexed I/O & Peripheral Pin PB5 (General)
136	PB6	I/O	Multiplexed I/O & Peripheral Pin PB6 (General)
137	PB7	I/O	Multiplexed I/O & Peripheral Pin PB7 (General)
138	BOOT0	I	Input-Only Pin BOOT0 (General)
139	PB8	I/O	Multiplexed I/O & Peripheral Pin PB8 (General)
140	PB9	I/O	Multiplexed I/O & Peripheral Pin PB9 (General)
141	PE0	I/O	Multiplexed I/O & Peripheral Pin PE0 (General)
142	PE1	I/O	Multiplexed I/O & Peripheral Pin PE1 (General)
143	PDR_ON	I/O	Multiplexed I/O & Peripheral Pin PDR_ON (General)
144	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))

PIN 1 PE2

I/O

Multiplexed I/O & Peripheral Pin PE2 (General)

Design note: Signal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 30 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

STM32F765ZIT7 (LQFP-144(20x20)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

STM32F765ZIT7 (LQFP-144(20x20)) - 2. Standard Pinout (Top View)

True package pinout (144 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

STM32F765ZIT7 (LQFP-144(20x20)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

STM32F765ZIT7 (LQFP-144(20x20)) - 4. Package Dimensions (D×E×A)

LQFP-144(20x20) · 20.00×20.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

STM32F765ZIT7 (LQFP-144(20x20)) - 5. Recommended Land Pattern

IPC-7351B Footprint (144 Pads)Expand ›

6. Application SchematicSCHEMATIC

STM32F765ZIT7 (LQFP-144(20x20)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (30 figures · Page 1/3)

Showing 1–12 of 30 uncropped original figures for STM32F765 / STM32F767 / STM32F769

P57 · p57_fig01EXACT PACKAGE

Figure 13. STM32F76xxx LQFP144 pinout

P227 · p227_fig01EXACT PACKAGE

Figure 90. LQFP144 recommended footprint

P1 · p01_fig01881×617px

• Low-power - Sleep, Stop and Standby modes - VBAT supply for RTC, 32×32 bit backup registers + 4 Kbytes backup SRAM

P57 · p57_fig01P57

Datasheet Page 57 (p57_fig01)

P62 · p62_fig011751×1689px

Figure 18. STM32F76xxx LQFP208 pinout

P66 · p66_fig011748×1076px

66/252 DS11532 Rev 7

P105 · p105_fig011546×2099px

Figure 24. STM32F769xx/STM32F779xx power supply scheme

P105 · p105_fig01P105

Datasheet Page 105 (p105_fig01)

P106 · p106_fig011551×2039px

Figure 25. STM32F765xx/STM32F767xx/STM32F777xx power supply scheme

P136 · p136_fig011546×487px

Figure 30. Typical application with an 8 MHz crystal

P227 · p227_fig01P227

Datasheet Page 227 (p227_fig01)

P237 · p237_fig011548×1332px

Figure 99. WLCSP180 recommended footprint

Page 1 / 3 (30 extracted figures)

Technical Specifications & Part Details (STM32F765ZIT7)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Embedded Microcontroller Unit (MCU)

Detailed Overview:STM32F765ZIT7 (LQFP-144(20x20)) is a 144-pin embedded microcontroller unit (mcu) featuring a 20.00 × 20.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.7 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA, CAN, DAC, RTC/CLK, SWD/JTAG, UART interfaces.

Operating Supply VoltageV_CC / V_DD

1.7 V to 3.6 V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

216 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

78 5V-tolerant (FT) pins detected

Package Envelope (D × E × A)D × E × A

20.00 × 20.00 × 1.60 mm (A1=0.10 mm)

Package family: LQFP (LQFP-144(20x20))

Pin Count & Lead PitchN / e

144 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA, CAN, DAC, RTC/CLK, SWD/JTAG, UART

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol144 auto-grouped pins

IPC-7351B Land Pattern144 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

ST·LQFP-144(20x20)

IPC-7351B

144P20.0×20.0×1.60mmP=0.5mm

STM32F765 / STM32F767 / STM32F769 (LQFP-144(20x20))

LQFP-144(20x20) · 144P

STM32F765ZIT6

IPC-7351B

180P5.5×6.0×0.56mmP=0.4mm

STM32F765 / STM32F767 / STM32F769 (WLCSP-180(5.5x6))

WLCSP-180(5.5x6) · 180P

STM32F769AIY6UTR

ST·WLCSP-180(5.5x6)

IPC-7351B

180P5.5×6.0×0.56mmP=0.4mm

STM32F765 / STM32F767 / STM32F769 (WLCSP-180(5.5x6))

Mechanical Dimensions & Land Pattern (LQFP-144(20x20))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

20.00 × 20.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.60mm · e=0.50mm

Pad Size (W × L)Level B

0.35 × 1.35 mm

Pins / Total PadsTopology

144P / 144Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit LQFP-144(20x20)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F765ZIT7 (LQFP-144(20x20))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F765ZIT7 (LQFP-144(20x20))?

Manufactured by ST, the STM32F765ZIT7 is housed in a LQFP-144(20x20) package with 144 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), 2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), 3 (PE4: Multiplexed I/O & Peripheral Pin PE4 (SPI)), 4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (SPI)), 5 (PE6: Multiplexed I/O & Peripheral Pin PE6 (SPI)), 6 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))).

What are the IPC-7351B PCB Footprint dimensions for STM32F765ZIT7?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F765ZIT7 (LQFP-144(20x20)) has a nominal body envelope of 20.00 × 20.00 mm, pitch e = 0.50 mm, and 144 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F765ZIT7?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F765ZIT7 (ST, LQFP-144(20x20)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (144 pins) & STM32F765 / STM32F767 / STM32F769 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	PE2	Digital_IO	Signal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
2	PE3	Digital_IO	Signal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
3	PE4	Digital_IO	Signal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSS. Supported peripheral buses: SPI.
4	PE5	Digital_IO	Signal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_SADFSDM1. Supported peripheral buses: SPI.
5	PE6	Digital_IO	Signal terminal PE6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MOSI. Supported peripheral buses: SPI.
6	VBAT	Power_In	Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
7	PC13	Digital_IO	Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
8	PC14- OSC32_IN	Digital_IO	Signal terminal PC14- OSC32_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14- OSC32_IN. Supported peripheral buses: RTC/CLK.
9	PC15- OSC32_OUT	Digital_IO	Signal terminal PC15- OSC32_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15- OSC32_OUT. Supported peripheral buses: RTC/CLK.
10	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
11	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
12	PH0- OSC_IN	Digital_IO	Signal terminal PH0- OSC_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0- OSC_IN. Supported peripheral buses: RTC/CLK.
13	PH1- OSC_OUT	Digital_IO	Signal terminal PH1- OSC_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1- OSC_OUT. Supported peripheral buses: RTC/CLK.
14	NRST	Digital_IO	Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
15	PC0	Digital_IO	Signal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
16	PC1	Digital_IO	Signal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_M. Supported peripheral buses: SPI, I2C, ADC, RTC/CLK.
17	PC2	Digital_IO	Signal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: SPI, ADC.
18	PC3	Digital_IO	Signal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC.
19	VSSA	GND	0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
20	VREF+	Analog	Signal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
21	VDDA	Power_In	Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
22	PA0- WKUP	Digital_IO	Signal terminal PA0- WKUP (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0- WKUP. Supported peripheral buses: UART, ADC.
23	PA1	Digital_IO	Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC.
24	PA2	Digital_IO	Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: SPI, ADC.
25	PA3	Digital_IO	Signal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: ADC.
26	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
27	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
28	PA4	Digital_IO	Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
29	PA5	Digital_IO	Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_CKSPI6. Supported peripheral buses: SPI, ADC, DAC.
30	PA6	Digital_IO	Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, SPI6_MISO. Supported peripheral buses: SPI, ADC.
31	PA7	Digital_IO	Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SDSPI6MOSI. Supported peripheral buses: SPI, ADC, PWM.
32	PC4	Digital_IO	Signal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: UART, ADC.
33	PC5	Digital_IO	Signal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: UART, ADC.
34	PB0	Digital_IO	Signal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
35	PB1	Digital_IO	Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
36	PB2	Digital_IO	Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SDQUADSPI. Supported peripheral buses: SPI, I2C.
37	PE7	Digital_IO	Signal terminal PE7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
38	PE8	Digital_IO	Signal terminal PE8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: PWM.
39	PE9	Digital_IO	Signal terminal PE9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE9. Supported peripheral buses: UART, PWM.
40	PE10	Digital_IO	Signal terminal PE10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE10. Supported peripheral buses: PWM.
41	PE11	Digital_IO	Signal terminal PE11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE11. Supported peripheral buses: SPI.
42	PE12	Digital_IO	Signal terminal PE12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE12. Supported peripheral buses: SPI.
43	PE13	Digital_IO	Signal terminal PE13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE13. Supported peripheral buses: SPI.
44	PE14	Digital_IO	Signal terminal PE14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MOSISAI2MCLK. Supported peripheral buses: SPI.
45	PE15	Digital_IO	Signal terminal PE15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE15. Supported peripheral buses: General.
46	PB10	Digital_IO	Signal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB10. Supported peripheral buses: UART, I2C.
47	PB11	Digital_IO	Signal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: UART, I2C.
48	VCAP_1	Digital_IO	Signal terminal VCAP_1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_1. Supported peripheral buses: General.
49	VSS	GND	Bottom exposed die attach pad (VSS) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
50	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
51	PB12	Digital_IO	Signal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: UART, SPI, I2C.
52	PB13	Digital_IO	Signal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_CKDFSDM1. Supported peripheral buses: UART, SPI, PWM.
53	PB14	Digital_IO	Signal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI.
54	PB15	Digital_IO	Signal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: UART, RTC/CLK.
55	PD8	Digital_IO	Signal terminal PD8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD8. Supported peripheral buses: UART.
56	PD9	Digital_IO	Signal terminal PD9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD9. Supported peripheral buses: General.
57	PD10	Digital_IO	Signal terminal PD10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General.
58	PD11	Digital_IO	Signal terminal PD11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD11. Supported peripheral buses: UART, I2C.
59	PD12	Digital_IO	Signal terminal PD12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General.
60	PD13	Digital_IO	Signal terminal PD13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: I2C, PWM.
61	PD14	Digital_IO	Signal terminal PD14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: UART.
62	PD15	Digital_IO	Signal terminal PD15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: UART.
63	PC6	Digital_IO	Signal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
64	PC7	Digital_IO	Signal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: PWM.

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