Mechanical Dimensions & Land Pattern (WLCSP-180(5.5x6))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
5.50 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
180P / 180Pad (BGA_GRID)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit WLCSP-180(5.5x6) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32F769AIY6TR (WLCSP-180(5.5x6))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32F769AIY6TR (WLCSP-180(5.5x6))?
Manufactured by ST, the STM32F769AIY6TR is housed in a WLCSP-180(5.5x6) package with 180 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: A1 (PC14- OSC32_IN: Multiplexed I/O & Peripheral Pin PC14- OSC32_IN (RTC/CLK)), A2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), A3 (PA3: Multiplexed I/O & Peripheral Pin PA3 (General)), A4 (PA4: Multiplexed I/O & Peripheral Pin PA4 (General)), A5 (PA5: Multiplexed I/O & Peripheral Pin PA5 (General)), A6 (PB4(NJTR ST): Multiplexed I/O & Peripheral Pin PB4(NJTR ST) (UART, SPI, SWD/JTAG)).
What are the IPC-7351B PCB Footprint dimensions for STM32F769AIY6TR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F769AIY6TR (WLCSP-180(5.5x6)) has a nominal body envelope of 6.00 × 5.50 mm, pitch e = 0.40 mm, and 180 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F769AIY6TR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F769AIY6TR (ST, WLCSP-180(5.5x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (180 pins) & STM32F765 / STM32F767 / STM32F769 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| A1 | PC14- OSC32_IN | Digital_IO | Signal terminal PC14- OSC32_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14- OSC32_IN. Supported peripheral buses: RTC/CLK. |
| A2 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| A3 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General. |
| A4 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General. |
| A5 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General. |
| A6 | PB4(NJTR ST) | Digital_IO | Signal terminal PB4(NJTR ST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, SPI3_, SPI6_MISO. Supported peripheral buses: UART, SPI, SWD/JTAG. |
| A7 | PB3 (JTDO / TRACESW O) | Digital_IO | Signal terminal PB3 (JTDO / TRACESW O) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_CKSPI3SCK, SPI6_SCK. Supported peripheral buses: UART, SPI, PWM, CAN, SWD/JTAG. |
| A8 | PA15(JTDI ) | Digital_IO | Signal terminal PA15(JTDI ) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_WSSPI3NSS, SPI6_NSS. Supported peripheral buses: UART, SPI, CAN, SWD/JTAG. |
| A9 | PA14(JTC K-SWCLK) | Digital_IO | Signal terminal PA14(JTC K-SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14(JTC K-SWCLK). Supported peripheral buses: SWD/JTAG. |
| A10 | PA13(JTM S-SWDIO) | Digital_IO | Signal terminal PA13(JTM S-SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13(JTM S-SWDIO). Supported peripheral buses: SWD/JTAG. |
| A11 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General. |
| A12 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General. |
| A13 | PA13 | Digital_IO | Signal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General. |
| B1 | PC15- OSC32_OUT | Digital_IO | Signal terminal PC15- OSC32_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15- OSC32_OUT. Supported peripheral buses: RTC/CLK. |
| B2 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| B3 | PB3 | Digital_IO | Signal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General. |
| B4 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General. |
| B5 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General. |
| B6 | PD5 | Digital_IO | Signal terminal PD5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: UART. |
| B7 | PD2 | Digital_IO | Signal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART. |
| B8 | PC11 | Digital_IO | Signal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISORX. Supported peripheral buses: SPI. |
| B9 | PC10 | Digital_IO | Signal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI. |
| B10 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_CKUART4TX. Supported peripheral buses: UART, SPI, CAN. |
| B11 | PB11 | Digital_IO | Signal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General. |
| B12 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General. |
| B13 | PB13 | Digital_IO | Signal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General. |
| C1 | PH0- OSC_IN | Digital_IO | Signal terminal PH0- OSC_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0- OSC_IN. Supported peripheral buses: RTC/CLK. |
| C2 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| C3 | PE4 | Digital_IO | Signal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSS. Supported peripheral buses: SPI. |
| C4 | PC4 | Digital_IO | Signal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General. |
| C5 | PC5 | Digital_IO | Signal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General. |
| C6 | PD6 | Digital_IO | Signal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: UART. |
| C7 | PD3 | Digital_IO | Signal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: UART. |
| C8 | PC12 | Digital_IO | Signal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SDUSART3. Supported peripheral buses: UART, SPI. |
| C9 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, I2C. |
| C10 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_WSUART4RX. Supported peripheral buses: UART, SPI, PWM. |
| C11 | PC11 | Digital_IO | Signal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General. |
| C12 | PC12 | Digital_IO | Signal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General. |
| C13 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General. |
| D1 | PH1- OSC_OUT | Digital_IO | Signal terminal PH1- OSC_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1- OSC_OUT. Supported peripheral buses: RTC/CLK. |
| D2 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| D3 | PE5 | Digital_IO | Signal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_SADFSDM1. Supported peripheral buses: SPI. |
| D4 | PD4 | Digital_IO | Signal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General. |
| D5 | PD5 | Digital_IO | Signal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General. |
| D6 | PD7 | Digital_IO | Signal terminal PD7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: UART. |
| D7 | PD4 | Digital_IO | Signal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General. |
| D8 | PD0 | Digital_IO | Signal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: UART. |
| D9 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, CAN, RTC/CLK. |
| D10 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART. |
| D11 | PD11 | Digital_IO | Signal terminal PD11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD11. Supported peripheral buses: General. |
| D12 | PD12 | Digital_IO | Signal terminal PD12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General. |
| D13 | PD13 | Digital_IO | Signal terminal PD13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General. |
| E1 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| E2 | PC2 | Digital_IO | Signal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: SPI, ADC. |
| E3 | PE6 | Digital_IO | Signal terminal PE6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MOSI. Supported peripheral buses: SPI. |
| E4 | PE4 | Digital_IO | Signal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General. |
| E5 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| E6 | BYPASS_REG | Digital_IO | Signal terminal BYPASS_REG (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: BYPASS_REG. Supported peripheral buses: General. |
| E7 | VCAP_2 | Digital_IO | Signal terminal VCAP_2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_2. Supported peripheral buses: General. |
| E8 | PD1 | Digital_IO | Signal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: UART. |
| E9 | PC9 | Digital_IO | Signal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: I2C, RTC/CLK. |
| E10 | PC7 | Digital_IO | Signal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: PWM. |
| E11 | PE11 | Digital_IO | Signal terminal PE11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE11. Supported peripheral buses: General. |
| E12 | PE12 | Digital_IO | Signal terminal PE12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE12. Supported peripheral buses: General. |