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TPS5430DDAR (SOIC-8-EP) — Symbol, Footprint IPC-7351B & 3D STEP Model

TPS5430DDAR

TIID: C9864SOIC-8-EP · 9 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · TPS5430DDAR (SOIC-8-EP)1BOOT2NC3NC4VSENSE5ENA9PowerPAD8PH7VIN6GNDGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.812.77.62.5-2.5-7.6-12.7mm
2. 2D FOOTPRINT
123456789E=3.90mm · Pitch e=1.27mmD=4.90mm-5-4-3-2-101234543210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.90mm × 4.90mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (9/9)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1BOOTI/OMultiplexed I/O & Peripheral Pin BOOT (General)
2NCI/OMultiplexed I/O & Peripheral Pin NC (General)
3NCI/OMultiplexed I/O & Peripheral Pin NC (General)
4VSENSEI/OMultiplexed I/O & Peripheral Pin VSENSE (General)
5ENAI/OMultiplexed I/O & Peripheral Pin ENA (General)
6GNDGNDGround Reference Pin (GND)
7VINPowerPower Supply Input (VIN — 5.5 V to 36 V)
8PHI/OMultiplexed I/O & Peripheral Pin PH (General)
9PowerPADI/OMultiplexed I/O & Peripheral Pin PowerPAD (General)
PIN 1 BOOT
I/O
Multiplexed I/O & Peripheral Pin BOOT (General)
Design note: Signal terminal BOOT (I/O, 5.5 V to 36 V domain). Multiplexed alternate functions: BOOT. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 23 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: TPS5430DDAR (TI · SOIC-8-EP)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
TPS5430DDAR (SOIC-8-EP) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
TPS5430DDAR (SOIC-8-EP) - 2. Standard Pinout (Top View)
True package pinout (9 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
TPS5430DDAR (SOIC-8-EP) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
TPS5430DDAR (SOIC-8-EP) - 4. Package Dimensions (D×E×A)
SOIC-8-EP · 3.90×4.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
TPS5430DDAR (SOIC-8-EP) - 5. Recommended Land Pattern
IPC-7351B Footprint (9 Pads)Expand ›
6. Application SchematicSCHEMATIC
TPS5430DDAR (SOIC-8-EP) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (23 figures · Page 1/2)
Showing 1–12 of 23 uncropped original figures for TPS5430
P1 · p01_fig012254×1198px
TPS5430DDAR (SOIC-8-EP) — TPS5431 5.5 V to 23 V
TPS5431 5.5 V to 23 V
P3 · p03_fig011362×992px
TPS5430DDAR (SOIC-8-EP) — 5 Pin Configuration and Functions
5 Pin Configuration and Functions
P3 · p03_fig01P3
TPS5430DDAR (SOIC-8-EP) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P13 · p13_fig012612×938px
TPS5430DDAR (SOIC-8-EP) — Figure 9. Application Circuit, 12 V Input to 5.0 V Output
Figure 9. Application Circuit, 12 V Input to 5.0 V Output
P13 · p13_fig022934×649px
TPS5430DDAR (SOIC-8-EP) — Figure 9. Application Circuit, 12 V Input to 5.0 V Output
Figure 9. Application Circuit, 12 V Input to 5.0 V Output
P21 · p21_fig012730×975px
TPS5430DDAR (SOIC-8-EP) — Figure 17. 10 V– 35 V Input to 5 V Output Application Circuit
Figure 17. 10 V– 35 V Input to 5 V Output Application Circuit
P21 · p21_fig022934×649px
TPS5430DDAR (SOIC-8-EP) — Figure 17. 10 V– 35 V Input to 5 V Output Application Circuit
Figure 17. 10 V– 35 V Input to 5 V Output Application Circuit
P22 · p22_fig012737×914px
TPS5430DDAR (SOIC-8-EP) — Figure 18. 9 V – 21 V Input to 5 V Output Application Circuit
Figure 18. 9 V – 21 V Input to 5 V Output Application Circuit
P22 · p22_fig022934×650px
TPS5430DDAR (SOIC-8-EP) — Figure 18. 9 V – 21 V Input to 5 V Output Application Circuit
Figure 18. 9 V – 21 V Input to 5 V Output Application Circuit
P22 · p22_fig01P22
TPS5430DDAR (SOIC-8-EP) — Datasheet Page 22 (p22_fig01)
Datasheet Page 22 (p22_fig01)
P23 · p23_fig01P23
TPS5430DDAR (SOIC-8-EP) — Datasheet Page 23 (p23_fig01)
Datasheet Page 23 (p23_fig01)
P28 · p28_fig012564×2653px
TPS5430DDAR (SOIC-8-EP) — PACKAGE OUTLINE
PACKAGE OUTLINE
Page 1 / 2 (23 extracted figures)

Technical Specifications & Part Details (TPS5430DDAR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:TPS5430DDAR (SOIC-8-EP) is a 8-pin standard electronic & interconnect component featuring a 4.90 × 3.90 × 1.70 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 5.5 V to 36 V supply operation across 40°C to 125°C with integrated PWM interfaces.
Operating Supply VoltageV_CC / V_DD
5.5 V to 36 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
40°C to 125°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
500 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.90 × 3.90 × 1.70 mm (A1=0.00 mm)
Package family: SOIC (SOIC-8-EP)
Pin Count & Lead PitchN / e
8 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol9 auto-grouped pins
OK
IPC-7351B Land Pattern9 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteEPAD 2.40×3.10mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOIC-8-EP)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.90 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.70mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.55 mm
Pins / Total PadsTopology
9P / 9Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOIC-8-EP
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — TPS5430DDAR (SOIC-8-EP)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of TPS5430DDAR (SOIC-8-EP)?

Manufactured by TI, the TPS5430DDAR is housed in a SOIC-8-EP package with 9 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 5.5 V to 36 V. Key pins include: 1 (BOOT: Multiplexed I/O & Peripheral Pin BOOT (General)), 2 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (VSENSE: Multiplexed I/O & Peripheral Pin VSENSE (General)), 5 (ENA: Multiplexed I/O & Peripheral Pin ENA (General)), 6 (GND: Ground Reference Pin (GND)).

What are the IPC-7351B PCB Footprint dimensions for TPS5430DDAR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), TPS5430DDAR (SOIC-8-EP) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.27 mm, and 9 copper pads plus a central exposed thermal pad (EPAD) of 2.40 × 3.10 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for TPS5430DDAR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for TPS5430DDAR (TI, SOIC-8-EP) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (9 pins) & TPS5430 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1BOOTDigital_IOSignal terminal BOOT (I/O, 5.5 V to 36 V domain). Multiplexed alternate functions: BOOT. Supported peripheral buses: General.
2NCDigital_IOSignal terminal NC (I/O, 5.5 V to 36 V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
3NCDigital_IOSignal terminal NC (I/O, 5.5 V to 36 V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
4VSENSEDigital_IOSignal terminal VSENSE (I/O, 5.5 V to 36 V domain). Multiplexed alternate functions: VSENSE. Supported peripheral buses: General.
5ENADigital_IOSignal terminal ENA (I/O, 5.5 V to 36 V domain). Multiplexed alternate functions: ENA. Supported peripheral buses: General.
6GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
7VINPower_InPrimary positive power supply input (VIN) operating in the 5.5 V to 36 V domain (Max rating: 36.0V).
8PHDigital_IOSignal terminal PH (I/O, 5.5 V to 36 V domain). Multiplexed alternate functions: PH. Supported peripheral buses: General.
9PowerPADDigital_IOSignal terminal PowerPAD (I/O, 5.5 V to 36 V domain). Multiplexed alternate functions: PowerPAD. Supported peripheral buses: General.
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