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PIC12C509A-04I/SM (SOIC-8-208mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC12C509A-04I/SM

MICROCHIPID: C9772SOIC-8-208mil · 8 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC12C509A-04I/SM (SOIC-8-208mil)1VDD2GP5/OSC1/CLK3GP4/OSC24GP3/MCLR/VPP8VSS7GP06GP15GP2/T0CKIGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.810.25.10-5.1-10.2mm
2. 2D FOOTPRINT
12345678E=5.30mm · Pitch e=1.27mmD=5.30mm-6-5-4-3-2-10123456543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.30mm × 5.30mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (8/8)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
2GP5/OSC1/CLKINI/OMultiplexed I/O & Peripheral Pin GP5/OSC1/CLKIN (RTC/CLK)
3GP4/OSC2I/OMultiplexed I/O & Peripheral Pin GP4/OSC2 (RTC/CLK)
4GP3/MCLR/VPPI/OMultiplexed I/O & Peripheral Pin GP3/MCLR/VPP (CAN)
5GP2/T0CKII/OMultiplexed I/O & Peripheral Pin GP2/T0CKI (CAN)
6GP1I/OMultiplexed I/O & Peripheral Pin GP1 (CAN)
7GP0I/OMultiplexed I/O & Peripheral Pin GP0 (CAN)
8VSSGNDGround Reference Pin (VSS)
PIN 1 VDD
Power
Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
Design note: PositivesupplyforlogicandI/Opins
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC12C509A-04I/SM (MICROCHIP · SOIC-8-208mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC12C509A-04I/SM (SOIC-8-208mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC12C509A-04I/SM (SOIC-8-208mil) - 2. Standard Pinout (Top View)
True package pinout (8 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC12C509A-04I/SM (SOIC-8-208mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC12C509A-04I/SM (SOIC-8-208mil) - 4. Package Dimensions (D×E×A)
SOIC-8-208mil · 5.30×5.30mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC12C509A-04I/SM (SOIC-8-208mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (8 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC12C509A-04I/SM (SOIC-8-208mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for PIC12C509A
P99 · p99_fig01EXACT PACKAGE
PIC12C509A-04I/SM (SOIC-8-208mil) — PIC12C5XX | 15.0 PACKAGING INFORMATION | 15.1 Package Marking Information | XXXXXXXX XXXXXCDE | AABB | 8-Lead PDIP (300 mil) Example | 8-Lead SOIC (208 mil) | XXXXXXX | AABBCDE XXXXXXX | 8-Lead Windowed Ceramic Side Brazed (300 mil) | XXXXX
PIC12C5XX | 15.0 PACKAGING INFORMATION | 15.1 Package Marking Information | XXXXXXXX XXXXXCDE | AABB | 8-Lead PDIP (300 mil) Example | 8-Lead SOIC (208 mil) | XXXXXXX | AABBCDE XXXXXXX | 8-Lead Windowed Ceramic Side Brazed (300 mil) | XXXXX
P1 · p01_fig01298×181px
PIC12C509A-04I/SM (SOIC-8-208mil) — 8-Pin, 8-Bit CMOS Microcontrollers
8-Pin, 8-Bit CMOS Microcontrollers
P46 · p46_fig01727×739px
PIC12C509A-04I/SM (SOIC-8-208mil) — FIGURE 8-16: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
FIGURE 8-16: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
P46 · p46_fig01P46
PIC12C509A-04I/SM (SOIC-8-208mil) — Datasheet Page 46 (p46_fig01)
Datasheet Page 46 (p46_fig01)
P47 · p47_fig011474×1456px
PIC12C509A-04I/SM (SOIC-8-208mil) — FIGURE 9-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 11 6 5 4 0
FIGURE 9-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 11 6 5 4 0
P99 · p99_fig021130×608px
PIC12C509A-04I/SM (SOIC-8-208mil) — XXXXXX
XXXXXX
P99 · p99_fig01P99
PIC12C509A-04I/SM (SOIC-8-208mil) — Datasheet Page 99 (p99_fig01)
Datasheet Page 99 (p99_fig01)
P101 · p101_fig011263×1570px
PIC12C509A-04I/SM (SOIC-8-208mil) — (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
P102 · p102_fig011264×1542px
PIC12C509A-04I/SM (SOIC-8-208mil) — (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
P2 · p02_fig01All Packages in PDF
PIC12C509A-04I/SM (SOIC-8-208mil) — VSS
VSS

Technical Specifications & Part Details (PIC12C509A-04I/SM)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC12C509A-04I/SM (SOIC-8-208mil) is a 8-pin standard electronic & interconnect component featuring a 5.30 × 5.30 × 1.90 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 0°C to +70°C with integrated CAN, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
0°C to +70°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
4 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.30 × 5.30 × 1.90 mm (A1=0.15 mm)
Package family: SOIC (SOIC-8-208mil)
Pin Count & Lead PitchN / e
8 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
CAN, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol8 auto-grouped pins
OK
IPC-7351B Land Pattern8 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOIC-8-208mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.30 × 5.30 mm
Height (A) & Pitch (e)IPC-7351B
A=1.90mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.95 mm
Pins / Total PadsTopology
8P / 8Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOIC-8-208mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC12C509A-04I/SM (SOIC-8-208mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC12C509A-04I/SM (SOIC-8-208mil)?

Manufactured by MICROCHIP, the PIC12C509A-04I/SM is housed in a SOIC-8-208mil package with 8 pins and a 1.27 mm lead pitch. Key pins include: 1 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 2 (GP5/OSC1/CLKIN: Multiplexed I/O & Peripheral Pin GP5/OSC1/CLKIN (RTC/CLK)), 3 (GP4/OSC2: Multiplexed I/O & Peripheral Pin GP4/OSC2 (RTC/CLK)), 4 (GP3/MCLR/VPP: Multiplexed I/O & Peripheral Pin GP3/MCLR/VPP (CAN)), 5 (GP2/T0CKI: Multiplexed I/O & Peripheral Pin GP2/T0CKI (CAN)), 6 (GP1: Multiplexed I/O & Peripheral Pin GP1 (CAN)).

What are the IPC-7351B PCB Footprint dimensions for PIC12C509A-04I/SM?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC12C509A-04I/SM (SOIC-8-208mil) has a nominal body envelope of 5.30 × 5.30 mm, pitch e = 1.27 mm, and 8 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC12C509A-04I/SM?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC12C509A-04I/SM (MICROCHIP, SOIC-8-208mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (8 pins) & PIC12C509A Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2GP5/OSC1/CLKINDigital_IOSignal terminal GP5/OSC1/CLKIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP5/OSC1/CLKIN. Supported peripheral buses: RTC/CLK.
3GP4/OSC2Digital_IOSignal terminal GP4/OSC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP4/OSC2. Supported peripheral buses: RTC/CLK.
4GP3/MCLR/VPPDigital_IOSignal terminal GP3/MCLR/VPP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP3/MCLR/VPP. Supported peripheral buses: CAN.
5GP2/T0CKIDigital_IOSignal terminal GP2/T0CKI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP2/T0CKI. Supported peripheral buses: CAN.
6GP1Digital_IOSignal terminal GP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP1. Supported peripheral buses: CAN.
7GP0Digital_IOSignal terminal GP0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP0. Supported peripheral buses: CAN.
8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
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