CH315H (SOP-18-300mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH315H

WCHID: C96509SOP-18-300mil · 18 Pins · Pitch 1.27mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH315H (SOP-18-300mil)1NC .2GND3UP#4LSI#5LSO#6VCC7GND8V39REF18GND17GND16VCC15OPIN14GND13VCC12UP#11VCC10GNDGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
123456789101112131415161718E=7.50mm · Pitch e=1.27mmD=11.55mm-8-6-4-20246897531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 7.50mm × 11.55mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (18/18)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1NC .I/OMultiplexed I/O & Peripheral Pin NC . (General)
2GNDGNDGround Reference Pin (GND)
3UP#I/OMultiplexed I/O & Peripheral Pin UP# (General)
4LSI#I/OMultiplexed I/O & Peripheral Pin LSI# (USB)
5LSO#I/OMultiplexed I/O & Peripheral Pin LSO# (USB)
6VCCPowerPower Supply Input (VCC — 3.3V to 5V)
7GNDGNDGround Reference Pin (GND)
8V3PowerRegulated Power Output (V3 — 3.3V to 5V)
9REFI/OMultiplexed I/O & Peripheral Pin REF (General)
10GNDGNDGround Reference Pin (GND)
11VCCPowerPower Supply Input (VCC — 3.3V to 5V)
12UP#I/OMultiplexed I/O & Peripheral Pin UP# (General)
13VCCPowerPower Supply Input (VCC — 3.3V to 5V)
14GNDGNDGround Reference Pin (GND)
15OPINI/OMultiplexed I/O & Peripheral Pin OPIN (General)
16VCCPowerPower Supply Input (VCC — 3.3V to 5V)
17GNDGNDGround Reference Pin (GND)
18GNDGNDGround Reference Pin (GND)
PIN 1 NC .
I/O
Multiplexed I/O & Peripheral Pin NC . (General)
Design note: 禁止连接
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH315H (WCH · SOP-18-300mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH315H (SOP-18-300mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH315H (SOP-18-300mil) - 2. Standard Pinout (Top View)
True package pinout (18 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH315H (SOP-18-300mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH315H (SOP-18-300mil) - 4. Package Dimensions (D×E×A)
SOP-18-300mil · 7.50×11.55mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH315H (SOP-18-300mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (18 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH315H (SOP-18-300mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH315
P2 · p02_fig01EXACT PACKAGE
CH315H (SOP-18-300mil) — 封装形式 塑体宽度 引脚间距 封装说明 订货型号 SOP14 3.9mm 150mil 1.27mm 50mil 标准的14 脚贴片 CH315G QFN20_3x3 3*3mm 0.4mm 15.7mil 四边无引线20 脚 CH315D SOP18 7.62mm 300mil 1.27mm 50mil 标准的宽18 脚贴片 CH315H
封装形式 塑体宽度 引脚间距 封装说明 订货型号 SOP14 3.9mm 150mil 1.27mm 50mil 标准的14 脚贴片 CH315G QFN20_3x3 3*3mm 0.4mm 15.7mil 四边无引线20 脚 CH315D SOP18 7.62mm 300mil 1.27mm 50mil 标准的宽18 脚贴片 CH315H
P1 · p01_fig011551×862px
CH315H (SOP-18-300mil) — 2、特点
2、特点
P2 · p02_fig01P2
CH315H (SOP-18-300mil) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P3 · p03_fig011726×1306px
CH315H (SOP-18-300mil) — 6.1. 绝对最大值(临界或者超过绝对最大值将可能导致芯片工作不正常甚至损坏)
6.1. 绝对最大值(临界或者超过绝对最大值将可能导致芯片工作不正常甚至损坏)
P4 · p04_fig011003×1068px
CH315H (SOP-18-300mil) — 在设计印刷线路板PCB 时,需要注意:退耦电容C11、C12、C13、C14、C15、C16 尽量靠近CH315G 的相连引脚;为地线和电源提供合理的路径和线宽;使USB 的D+和D-信号线贴近平行布线,使XD+ 和XD-信号线贴近平行布线,尽量在两侧提供地线或者覆铜,减少来自外界的信号干扰。 rz CF C12 Cit uz cH3156 iu H.iu @.iu 4 YOo 188K Lstucc ur#_té I REF = Wa = he, END USE GND +
在设计印刷线路板PCB 时,需要注意:退耦电容C11、C12、C13、C14、C15、C16 尽量靠近CH315G 的相连引脚;为地线和电源提供合理的路径和线宽;使USB 的D+和D-信号线贴近平行布线,使XD+ 和XD-信号线贴近平行布线,尽量在两侧提供地线或者覆铜,减少来自外界的信号干扰。 rz CF C12 Cit uz cH3156 iu H.iu @.iu 4 YOo 188K Lstucc ur#_té I REF = Wa = he, END USE GND +
P4 · p04_fig01P4
CH315H (SOP-18-300mil) — Datasheet Page 4 (p04_fig01)
Datasheet Page 4 (p04_fig01)

Technical Specifications & Part Details (CH315H)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH315H (SOP-18-300mil) is a 18-pin standard electronic & interconnect component featuring a 11.55 × 7.50 × 2.50 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 3.3V to 5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB interfaces.
Operating Supply VoltageV_CC / V_DD
3.3V to 5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
11.55 × 7.50 × 2.50 mm (A1=0.20 mm)
Package family: SOP (SOP-18-300mil)
Pin Count & Lead PitchN / e
18 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol18 auto-grouped pins
OK
IPC-7351B Land Pattern18 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOP-18-300mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
11.55 × 7.50 mm
Height (A) & Pitch (e)IPC-7351B
A=2.50mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.90 mm
Pins / Total PadsTopology
18P / 18Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOP-18-300mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH315H (SOP-18-300mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH315H (SOP-18-300mil)?

Manufactured by WCH, the CH315H is housed in a SOP-18-300mil package with 18 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 3.3V to 5V. Key pins include: 1 (NC .: Multiplexed I/O & Peripheral Pin NC . (General)), 2 (GND: Ground Reference Pin (GND)), 3 (UP#: Multiplexed I/O & Peripheral Pin UP# (General)), 4 (LSI#: Multiplexed I/O & Peripheral Pin LSI# (USB)), 5 (LSO#: Multiplexed I/O & Peripheral Pin LSO# (USB)), 6 (VCC: Power Supply Input (VCC — 3.3V to 5V)).

What are the IPC-7351B PCB Footprint dimensions for CH315H?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH315H (SOP-18-300mil) has a nominal body envelope of 7.50 × 11.55 mm, pitch e = 1.27 mm, and 18 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH315H?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH315H (WCH, SOP-18-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (18 pins) & CH315 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1NC .Digital_IOSignal terminal NC . (I/O, 3.3V to 5V domain). Multiplexed alternate functions: NC .. Supported peripheral buses: General.
2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3UP#Digital_IOSignal terminal UP# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UP#. Supported peripheral buses: General.
4LSI#Digital_IOSignal terminal LSI# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: LSI#. Supported peripheral buses: USB.
5LSO#Digital_IOSignal terminal LSO# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: LSO#. Supported peripheral buses: USB.
6VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V to 5V domain (Max rating: 5.0V).
7GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
8V3Power_OutRegulated power output rail (V3) operating in the 3.3V to 5V domain (Max rating: 5.0V).
9REFDigital_IOSignal terminal REF (I/O, 3.3V to 5V domain). Multiplexed alternate functions: REF. Supported peripheral buses: General.
10GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
11VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V to 5V domain (Max rating: 5.0V).
12UP#Digital_IOSignal terminal UP# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UP#. Supported peripheral buses: General.
13VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V to 5V domain (Max rating: 5.0V).
14GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
15OPINDigital_IOSignal terminal OPIN (I/O, 3.3V to 5V domain). Multiplexed alternate functions: OPIN. Supported peripheral buses: General.
16VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V to 5V domain (Max rating: 5.0V).
17GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
18GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.