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CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CP2102N-A02-GQFN28R

SILICON LABSID: C964632QFN-28-EP(5x5) · 29 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CP2102N-A02-GQFN28R (QFN-28-EP(5x5))1DCD2RI/ CLK3GND4D+5D -6VDD7VREGIN8VBUS9RSTb10NC11SUSPENDb12SUSPEND13CHREN14CHR115CHR029EP28DTR27DSR26TXD25RXD24RTS23CTS22GPIO4 .21GPIO5 .20GPIO6 .19GPIO0/ . TXT18GPIO1/ . RXT17GPIO2/ . RS416GPIO3/ . WAKGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.825.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=5.00mm · Pitch e=0.50mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1DCDI/OMultiplexed I/O & Peripheral Pin DCD (General)
2RI/ CLKI/OMultiplexed I/O & Peripheral Pin RI/ CLK (General)
3GNDGNDGround Reference Pin (GND)
4D+I/OMultiplexed I/O & Peripheral Pin D+ (USB)
5D -I/OMultiplexed I/O & Peripheral Pin D - (USB)
6VDDPowerRegulated Power Output (VDD — 3.3V / 5.0V Standard Logic)
7VREGINI/OMultiplexed I/O & Peripheral Pin VREGIN (General)
8VBUSPowerPower Supply Input (VBUS — 3.3V / 5.0V Standard Logic)
9RSTbI/OMultiplexed I/O & Peripheral Pin RSTb (General)
10NCI/OMultiplexed I/O & Peripheral Pin NC (General)
11SUSPENDbI/OMultiplexed I/O & Peripheral Pin SUSPENDb (General)
12SUSPENDI/OMultiplexed I/O & Peripheral Pin SUSPEND (General)
13CHRENI/OMultiplexed I/O & Peripheral Pin CHREN (General)
14CHR1I/OMultiplexed I/O & Peripheral Pin CHR1 (General)
15CHR0I/OMultiplexed I/O & Peripheral Pin CHR0 (General)
16GPIO3/ . WAKEUPI/OMultiplexed I/O & Peripheral Pin GPIO3/ . WAKEUP (General)
17GPIO2/ . RS485I/OMultiplexed I/O & Peripheral Pin GPIO2/ . RS485 (General)
18GPIO1/ . RXTI/OMultiplexed I/O & Peripheral Pin GPIO1/ . RXT (General)
19GPIO0/ . TXTI/OMultiplexed I/O & Peripheral Pin GPIO0/ . TXT (General)
20GPIO6 .I/OMultiplexed I/O & Peripheral Pin GPIO6 . (General)
21GPIO5 .I/OMultiplexed I/O & Peripheral Pin GPIO5 . (General)
22GPIO4 .I/OMultiplexed I/O & Peripheral Pin GPIO4 . (General)
23CTSI/OMultiplexed I/O & Peripheral Pin CTS (UART)
24RTSI/OMultiplexed I/O & Peripheral Pin RTS (UART)
25RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
26TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
27DSRI/OMultiplexed I/O & Peripheral Pin DSR (UART)
28DTRI/OMultiplexed I/O & Peripheral Pin DTR (UART)
29EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 DCD
I/O
Multiplexed I/O & Peripheral Pin DCD (General)
Design note: DigitalInput DataCarrierDetectcontrolinput(activelow) . .
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 23 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CP2102N-A02-GQFN28R (SILICON LABS · QFN-28-EP(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) - 4. Package Dimensions (D×E×A)
QFN-28-EP(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (23 figures · Page 1/2)
Showing 1–12 of 23 uncropped original figures for CP2102N
P2 · p02_fig01EXACT PACKAGE
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) — Figure 1.1. CP2102N Part Numbering
Figure 1.1. CP2102N Part Numbering
P2 · p02_fig02EXACT PACKAGE
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) — silabs.com | Building a more connected world. Rev. 1.5 | 2
silabs.com | Building a more connected world. Rev. 1.5 | 2
P27 · p27_fig01EXACT PACKAGE
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) — Figure 5.1. CP2102N QFN28 Pinout
Figure 5.1. CP2102N QFN28 Pinout
P33 · p33_fig01EXACT PACKAGE
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) — Figure 6.1. QFN28 Package Drawing
Figure 6.1. QFN28 Package Drawing
P36 · p36_fig01EXACT PACKAGE
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) — Figure 6.3. QFN28 Package Marking
Figure 6.3. QFN28 Package Marking
P1 · p01_fig01401×236px
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) — USBXpress™ Family CP2102N Data Sheet
USBXpress™ Family CP2102N Data Sheet
P1 · p01_fig021611×760px
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) — • POS terminals • USB dongles • Gaming controllers
• POS terminals • USB dongles • Gaming controllers
P5 · p05_fig011048×832px
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) — Figure 2.1. Connection Diagram with Voltage Regulator Used and USB Connected (Bus-Powered)
Figure 2.1. Connection Diagram with Voltage Regulator Used and USB Connected (Bus-Powered)
P5 · p05_fig021360×832px
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) — Figure 2.2. Connection Diagram with Voltage Regulator Used and USB Connected (Self-Powered)
Figure 2.2. Connection Diagram with Voltage Regulator Used and USB Connected (Self-Powered)
P5 · p05_fig02P5
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) — Datasheet Page 5 (p05_fig02)
Datasheet Page 5 (p05_fig02)
P6 · p06_fig011068×761px
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) — Figure 2.3. Connection Diagram with Voltage Regulator Not Used
Figure 2.3. Connection Diagram with Voltage Regulator Not Used
P7 · p07_fig01P7
CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) — Datasheet Page 7 (p07_fig01)
Datasheet Page 7 (p07_fig01)
Page 1 / 2 (23 extracted figures)

Technical Specifications & Part Details (CP2102N-A02-GQFN28R)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) is a 28-pin standard electronic & interconnect component featuring a 5.00 × 5.00 × 0.75 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
48 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.75 mm (A1=0.05 mm)
Package family: QFN (QFN-28-EP(5x5))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.25×3.25mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28-EP(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.75mm · e=0.50mm
Pad Size (W × L)Level B
0.29 × 0.95 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28-EP(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CP2102N-A02-GQFN28R (QFN-28-EP(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CP2102N-A02-GQFN28R (QFN-28-EP(5x5))?

Manufactured by SILICON LABS, the CP2102N-A02-GQFN28R is housed in a QFN-28-EP(5x5) package with 29 pins and a 0.50 mm lead pitch. Key pins include: 1 (DCD: Multiplexed I/O & Peripheral Pin DCD (General)), 2 (RI/ CLK: Multiplexed I/O & Peripheral Pin RI/ CLK (General)), 3 (GND: Ground Reference Pin (GND)), 4 (D+: Multiplexed I/O & Peripheral Pin D+ (USB)), 5 (D -: Multiplexed I/O & Peripheral Pin D - (USB)), 6 (VDD: Regulated Power Output (VDD — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for CP2102N-A02-GQFN28R?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CP2102N-A02-GQFN28R (QFN-28-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 3.25 × 3.25 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CP2102N-A02-GQFN28R?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CP2102N-A02-GQFN28R (SILICON LABS, QFN-28-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & CP2102N Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1DCDDigital_IOSignal terminal DCD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD. Supported peripheral buses: General.
2RI/ CLKDigital_IOSignal terminal RI/ CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI/ CLK. Supported peripheral buses: General.
3GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
4D+Digital_IOSignal terminal D+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D+. Supported peripheral buses: USB.
5D -Digital_IOSignal terminal D - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D -. Supported peripheral buses: USB.
6VDDPower_OutRegulated power output rail (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
7VREGINDigital_IOSignal terminal VREGIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VREGIN. Supported peripheral buses: General.
8VBUSPower_InPrimary positive power supply input (VBUS) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9RSTbDigital_IOSignal terminal RSTb (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTb. Supported peripheral buses: General.
10NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
11SUSPENDbDigital_IOSignal terminal SUSPENDb (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SUSPENDb. Supported peripheral buses: General.
12SUSPENDDigital_IOSignal terminal SUSPEND (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SUSPEND. Supported peripheral buses: General.
13CHRENDigital_IOSignal terminal CHREN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CHREN. Supported peripheral buses: General.
14CHR1Digital_IOSignal terminal CHR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CHR1. Supported peripheral buses: General.
15CHR0Digital_IOSignal terminal CHR0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CHR0. Supported peripheral buses: General.
16GPIO3/ . WAKEUPDigital_IOSignal terminal GPIO3/ . WAKEUP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO3/ . WAKEUP. Supported peripheral buses: General.
17GPIO2/ . RS485Digital_IOSignal terminal GPIO2/ . RS485 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO2/ . RS485. Supported peripheral buses: General.
18GPIO1/ . RXTDigital_IOSignal terminal GPIO1/ . RXT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO1/ . RXT. Supported peripheral buses: General.
19GPIO0/ . TXTDigital_IOSignal terminal GPIO0/ . TXT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO0/ . TXT. Supported peripheral buses: General.
20GPIO6 .Digital_IOSignal terminal GPIO6 . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO6 .. Supported peripheral buses: General.
21GPIO5 .Digital_IOSignal terminal GPIO5 . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO5 .. Supported peripheral buses: General.
22GPIO4 .Digital_IOSignal terminal GPIO4 . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO4 .. Supported peripheral buses: General.
23CTSDigital_IOSignal terminal CTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS. Supported peripheral buses: UART.
24RTSDigital_IOSignal terminal RTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS. Supported peripheral buses: UART.
25RXDDigital_IOSignal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
26TXDDigital_IOSignal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
27DSRDigital_IOSignal terminal DSR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR. Supported peripheral buses: UART.
28DTRDigital_IOSignal terminal DTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR. Supported peripheral buses: UART.
29EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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