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C882045 (LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL) — Symbol, Footprint IPC-7351B & 3D STEP Model

C882045

SemiconductorLQFP-64_L10.0-W10.0-P0.50-LS12.0-BL · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C882045 (LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL)1VBAT2PC133PC14-OSC32_I4PC15-OSC32_O5PH0-OSC_IN(P6PH1-OSC_OUT(7NRST8PC09PC110PC211PC312VSSA/VREF-13VDDA/VREF+14PA015PA116PA217PA318VSS19VDD20PA421PA522PA623PA724PC425PC526PB027PB128PB229PB1030VCAP131VSS32VDD64VDD63VSS62PB961PB860BOOT059PB758PB657PB556PB4(NJTRST)55PB3(JTDO-SWO54PD253PC1252PC1151PC1050PA15 (JTDI)49PA14 (JTCKSW48VDD47VSS46PA13 (JTMSSW45PA1244PA1143PA1042PA941PA840PC939PC838PC737PC636PB1535PB1434PB1333PB12Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.245.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=10.00mm · Pitch e=0.50mmD=10.00mm-9-7-5-3-11357997531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
3PC14-OSC32_IN(PC14)I/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN(PC14) (RTC/CLK)
4PC15-OSC32_OUT(PC15)I/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT(PC15) (RTC/CLK)
5PH0-OSC_IN(PH0)I/OMultiplexed I/O & Peripheral Pin PH0-OSC_IN(PH0) (RTC/CLK)
6PH1-OSC_OUT(PH1)I/OMultiplexed I/O & Peripheral Pin PH1-OSC_OUT(PH1) (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
9PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
10PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
11PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
12VSSA/VREF-GNDGround Reference Pin (VSSA/VREF-)
13VDDA/VREF+PowerPower Supply Input (VDDA/VREF+ — 3.3V / 5.0V Standard Logic)
14PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
15PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
16PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
17PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
18VSSGNDGround Reference Pin (VSS)
19VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
20PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
21PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
22PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
23PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
24PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
25PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
26PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
27PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
28PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
29PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
30VCAP1I/OMultiplexed I/O & Peripheral Pin VCAP1 (General)
31VSSGNDGround Reference Pin (VSS)
32VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
33PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
34PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
35PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
36PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
37PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
38PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
39PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
40PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
41PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
42PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
43PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
44PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
45PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
46PA13 (JTMSSWDIO)I/OMultiplexed I/O & Peripheral Pin PA13 (JTMSSWDIO) (SWD/JTAG)
47VSSGNDGround Reference Pin (VSS)
48VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
49PA14 (JTCKSWCLK)I/OMultiplexed I/O & Peripheral Pin PA14 (JTCKSWCLK) (SWD/JTAG)
50PA15 (JTDI)I/OMultiplexed I/O & Peripheral Pin PA15 (JTDI) (SWD/JTAG)
51PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
52PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
53PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
54PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
55PB3(JTDO-SWO)I/OMultiplexed I/O & Peripheral Pin PB3(JTDO-SWO) (SWD/JTAG)
56PB4(NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4(NJTRST) (SWD/JTAG)
57PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
58PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
59PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
60BOOT0IInput-Only Pin BOOT0 (General)
61PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
62PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
63VSSGNDGround Reference Pin (VSS)
64VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C882045 (Semiconductor · LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C882045 (LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C882045 (LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C882045 (LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C882045 (LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL) - 4. Package Dimensions (D×E×A)
LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL · 10.00×10.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
C882045 (LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
C882045 (LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C882045)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C882045 (LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL) is a 64-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL)
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C882045 (LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C882045 (LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL)?

Manufactured by Semiconductor, the C882045 is housed in a LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL package with 64 pins and a 0.50 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (General)), 3 (PC14-OSC32_IN(PC14): Multiplexed I/O & Peripheral Pin PC14-OSC32_IN(PC14) (RTC/CLK)), 4 (PC15-OSC32_OUT(PC15): Multiplexed I/O & Peripheral Pin PC15-OSC32_OUT(PC15) (RTC/CLK)), 5 (PH0-OSC_IN(PH0): Multiplexed I/O & Peripheral Pin PH0-OSC_IN(PH0) (RTC/CLK)), 6 (PH1-OSC_OUT(PH1): Multiplexed I/O & Peripheral Pin PH1-OSC_OUT(PH1) (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for C882045?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C882045 (LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C882045?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C882045 (Semiconductor, LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & STM32F401 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
3PC14-OSC32_IN(PC14)Digital_IOSignal terminal PC14-OSC32_IN(PC14) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14-OSC32_IN(PC14). Supported peripheral buses: RTC/CLK.
4PC15-OSC32_OUT(PC15)Digital_IOSignal terminal PC15-OSC32_OUT(PC15) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15-OSC32_OUT(PC15). Supported peripheral buses: RTC/CLK.
5PH0-OSC_IN(PH0)Digital_IOSignal terminal PH0-OSC_IN(PH0) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PH0-OSC_IN(PH0). Supported peripheral buses: RTC/CLK.
6PH1-OSC_OUT(PH1)Digital_IOSignal terminal PH1-OSC_OUT(PH1) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PH1-OSC_OUT(PH1). Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8PC0Digital_IOSignal terminal PC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
9PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
10PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
11PC3Digital_IOSignal terminal PC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
12VSSA/VREF-GND0V electrical ground return terminal (VSSA/VREF-) for internal core logic, I/O drivers, and analog sub-blocks.
13VDDA/VREF+Power_InPrimary positive power supply input (VDDA/VREF+) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14PA0Digital_IOSignal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
15PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
16PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
17PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
18VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
19VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
20PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
21PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
22PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
23PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
24PC4Digital_IOSignal terminal PC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
25PC5Digital_IOSignal terminal PC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
26PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
27PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
28PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
29PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
30VCAP1Digital_IOSignal terminal VCAP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCAP1. Supported peripheral buses: General.
31VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
33PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
34PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
35PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
36PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
37PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
38PC7Digital_IOSignal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
39PC8Digital_IOSignal terminal PC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
40PC9Digital_IOSignal terminal PC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
41PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
42PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
43PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
44PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
45PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
46PA13 (JTMSSWDIO)Digital_IOSignal terminal PA13 (JTMSSWDIO) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13 (JTMSSWDIO). Supported peripheral buses: SWD/JTAG.
47VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
48VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
49PA14 (JTCKSWCLK)Digital_IOSignal terminal PA14 (JTCKSWCLK) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14 (JTCKSWCLK). Supported peripheral buses: SWD/JTAG.
50PA15 (JTDI)Digital_IOSignal terminal PA15 (JTDI) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15 (JTDI). Supported peripheral buses: SWD/JTAG.
51PC10Digital_IOSignal terminal PC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
52PC11Digital_IOSignal terminal PC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
53PC12Digital_IOSignal terminal PC12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
54PD2Digital_IOSignal terminal PD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
55PB3(JTDO-SWO)Digital_IOSignal terminal PB3(JTDO-SWO) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3(JTDO-SWO). Supported peripheral buses: SWD/JTAG.
56PB4(NJTRST)Digital_IOSignal terminal PB4(NJTRST) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4(NJTRST). Supported peripheral buses: SWD/JTAG.
57PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
58PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
59PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
60BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
61PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
62PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
63VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
64VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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