Mechanical Dimensions & Land Pattern (SOT-23-8)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SOT-23-8 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — INA219AIDCNR (SOT-23-8)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of INA219AIDCNR (SOT-23-8)?
Manufactured by TI, the INA219AIDCNR is housed in a SOT-23-8 package with 8 pins and a 0.65 mm lead pitch. Key pins include: 1 (IN+: Multiplexed I/O & Peripheral Pin IN+ (General)), 2 (IN –: Multiplexed I/O & Peripheral Pin IN – (General)), 3 (GND: Ground Reference Pin (GND)), 4 (VS: Multiplexed I/O & Peripheral Pin VS (General)), 5 (SCL: Multiplexed I/O & Peripheral Pin SCL (I2C)), 6 (SDA: Multiplexed I/O & Peripheral Pin SDA (I2C)).
What are the IPC-7351B PCB Footprint dimensions for INA219AIDCNR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), INA219AIDCNR (SOT-23-8) has a nominal body envelope of 1.60 × 2.90 mm, pitch e = 0.65 mm, and 8 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for INA219AIDCNR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for INA219AIDCNR (TI, SOT-23-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (8 pins) & INA219 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | IN+ | Digital_IO | Signal terminal IN+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IN+. Supported peripheral buses: General. |
| 2 | IN – | Digital_IO | Signal terminal IN – (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IN –. Supported peripheral buses: General. |
| 3 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 4 | VS | Digital_IO | Signal terminal VS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VS. Supported peripheral buses: General. |
| 5 | SCL | Digital_IO | Signal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C. |
| 6 | SDA | Digital_IO | Signal terminal SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C. |
| 7 | A0 | Digital_IO | Signal terminal A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0. Supported peripheral buses: General. |
| 8 | A1 | Digital_IO | Signal terminal A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1. Supported peripheral buses: General. |












