QFN-32-EP(5x5) · 33P
Synchronized Pinout (Symbol / 2D / 3D) (33/33)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | VDDK | Power | Power Supply Input (VDDK — 3.3V / 5.0V Standard Logic) |
| 2 | RSVD. | I/O | Multiplexed I/O & Peripheral Pin RSVD. (General) |
| 3 | MDIRP | I/O | Multiplexed I/O & Peripheral Pin MDIRP (General) |
| 4 | MDIRN | I/O | Multiplexed I/O & Peripheral Pin MDIRN (General) |
| 5 | GND | GND | Ground Reference Pin (GND) |
| 6 | MDITP | I/O | Multiplexed I/O & Peripheral Pin MDITP (General) |
| 7 | MDITN | I/O | Multiplexed I/O & Peripheral Pin MDITN (General) |
| 8 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 9 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 10 | GPIO1 | I/O | Multiplexed I/O & Peripheral Pin GPIO1 (General) |
| 11 | EEDIO | I/O | Multiplexed I/O & Peripheral Pin EEDIO (General) |
| 12 | EECK | I/O | Multiplexed I/O & Peripheral Pin EECK (General) |
| 13 | EECS | I/O | Multiplexed I/O & Peripheral Pin EECS (General) |
| 14 | WOL | I/O | Multiplexed I/O & Peripheral Pin WOL (General) |
| 15 | AVDD33 | Power | Power Supply Input (AVDD33 — 3.3V / 5.0V Standard Logic) |
| 16 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 17 | SCS | I/O | Multiplexed I/O & Peripheral Pin SCS (General) |
| 18 | SCK | I/O | Multiplexed I/O & Peripheral Pin SCK (SPI) |
| 19 | SDI/MOSI | I/O | Multiplexed I/O & Peripheral Pin SDI/MOSI (SPI) |
| 20 | SDO/MISO | I/O | Multiplexed I/O & Peripheral Pin SDO/MISO (SPI) |
| 21 | VDDIO | Power | Power Supply Input (VDDIO — 3.3V / 5.0V Standard Logic) |
| 22 | NC. | I/O | Multiplexed I/O & Peripheral Pin NC. (General) |
| 23 | GPIO2 | I/O | Multiplexed I/O & Peripheral Pin GPIO2 (General) |
| 24 | INT | I/O | Multiplexed I/O & Peripheral Pin INT (General) |
| 25 | LED2ACT | I/O | Multiplexed I/O & Peripheral Pin LED2ACT (General) |
| 26 | LED1SPD | I/O | Multiplexed I/O & Peripheral Pin LED1SPD (General) |
| 27 | RSTB | I/O | Multiplexed I/O & Peripheral Pin RSTB (General) |
| 28 | GPIO3 | I/O | Multiplexed I/O & Peripheral Pin GPIO3 (General) |
| 29 | AVDD33 | Power | Power Supply Input (AVDD33 — 3.3V / 5.0V Standard Logic) |
| 30 | XI | I/O | Multiplexed I/O & Peripheral Pin XI (RTC/CLK) |
| 31 | XO | I/O | Multiplexed I/O & Peripheral Pin XO (RTC/CLK) |
| 32 | GND | GND | Ground Reference Pin (GND) |
| 33 | GND | GND | Ground Reference Pin (GND) |
PIN 1 VDDK
PowerPower Supply Input (VDDK — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN-32-EP(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for CH390
P1 · p01_fig01248×133px
P1 · p01_fig021739×1053px
P2 · p02_fig011731×2095px
P2 · p02_fig01P2
P3 · p03_fig011929×2637px
P34 · p34_fig011390×1386px
P34 · p34_fig01P34
P35 · p35_fig011724×1637px
P36 · p36_fig011493×1045px
P36 · p36_fig02927×488px
Technical Specifications & Part Details (CH390H)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH390H (QFN-32-EP(5x5)) is a 32-pin standard electronic & interconnect component featuring a 5.00 × 5.00 × 1.00 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
72
MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (QFN-32-EP(5x5))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol33 auto-grouped pins
IPC-7351B Land Pattern33 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteEPAD 3.50×3.50mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH390 (2)
LQFP-48(7x7) · 48P
Mechanical Dimensions & Land Pattern (QFN-32-EP(5x5))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-32-EP(5x5) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH390H (QFN-32-EP(5x5))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH390H (QFN-32-EP(5x5))?
Manufactured by WCH, the CH390H is housed in a QFN-32-EP(5x5) package with 33 pins and a 0.50 mm lead pitch. Key pins include: 1 (VDDK: Power Supply Input (VDDK — 3.3V / 5.0V Standard Logic)), 2 (RSVD.: Multiplexed I/O & Peripheral Pin RSVD. (General)), 3 (MDIRP: Multiplexed I/O & Peripheral Pin MDIRP (General)), 4 (MDIRN: Multiplexed I/O & Peripheral Pin MDIRN (General)), 5 (GND: Ground Reference Pin (GND)), 6 (MDITP: Multiplexed I/O & Peripheral Pin MDITP (General)).
What are the IPC-7351B PCB Footprint dimensions for CH390H?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH390H (QFN-32-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.50 × 3.50 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH390H?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH390H (WCH, QFN-32-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (33 pins) & CH390 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VDDK | Power_In | Primary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 2 | RSVD. | Digital_IO | Signal terminal RSVD. (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD.. Supported peripheral buses: General. |
| 3 | MDIRP | Digital_IO | Signal terminal MDIRP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRP. Supported peripheral buses: General. |
| 4 | MDIRN | Digital_IO | Signal terminal MDIRN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRN. Supported peripheral buses: General. |
| 5 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 6 | MDITP | Digital_IO | Signal terminal MDITP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITP. Supported peripheral buses: General. |
| 7 | MDITN | Digital_IO | Signal terminal MDITN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITN. Supported peripheral buses: General. |
| 8 | NC. | Digital_IO | Signal terminal NC. (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 9 | NC. | Digital_IO | Signal terminal NC. (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 10 | GPIO1 | Digital_IO | Signal terminal GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO1. Supported peripheral buses: General. |
| 11 | EEDIO | Digital_IO | Signal terminal EEDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EEDIO. Supported peripheral buses: General. |
| 12 | EECK | Digital_IO | Signal terminal EECK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EECK. Supported peripheral buses: General. |
| 13 | EECS | Digital_IO | Signal terminal EECS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EECS. Supported peripheral buses: General. |
| 14 | WOL | Digital_IO | Signal terminal WOL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WOL. Supported peripheral buses: General. |
| 15 | AVDD33 | Power_In | Primary positive power supply input (AVDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 16 | NC. | Digital_IO | Signal terminal NC. (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 17 | SCS | Digital_IO | Signal terminal SCS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS. Supported peripheral buses: General. |
| 18 | SCK | Digital_IO | Signal terminal SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCK. Supported peripheral buses: SPI. |
| 19 | SDI/MOSI | Digital_IO | Signal terminal SDI/MOSI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDI/MOSI. Supported peripheral buses: SPI. |
| 20 | SDO/MISO | Digital_IO | Signal terminal SDO/MISO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDO/MISO. Supported peripheral buses: SPI. |
| 21 | VDDIO | Power_In | Primary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 22 | NC. | Digital_IO | Signal terminal NC. (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General. |
| 23 | GPIO2 | Digital_IO | Signal terminal GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General. |
| 24 | INT | Digital_IO | Signal terminal INT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT. Supported peripheral buses: General. |
| 25 | LED2ACT | Digital_IO | Signal terminal LED2ACT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED2ACT. Supported peripheral buses: General. |
| 26 | LED1SPD | Digital_IO | Signal terminal LED1SPD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED1SPD. Supported peripheral buses: General. |
| 27 | RSTB | Digital_IO | Signal terminal RSTB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTB. Supported peripheral buses: General. |
| 28 | GPIO3 | Digital_IO | Signal terminal GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General. |
| 29 | AVDD33 | Power_In | Primary positive power supply input (AVDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 30 | XI | Digital_IO | Signal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK. |
| 31 | XO | Digital_IO | Signal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK. |
| 32 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 33 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |