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JAN2N6383 (TO-204AA(TO-3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

JAN2N6383

MICROCHIPID: C7290741TO-204AA(TO-3) · 4 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · JAN2N6383 (TO-204AA(TO-3))1B2E4C3CGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.210.25.10-5.1-10.2mm
2. 2D FOOTPRINT
1234E=26.70mm · Pitch e=0.50mmD=39.40mm-24-22-20-18-16-14-12-10-8-6-4-2024681012141618202224302826242220181614121086420-2-4-6-8-10-12-14-16-18-20-22-24-26-28-30mm
3. 3D CAD MODEL
Package Body: 26.70mm × 39.40mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (4/4)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1BI/OMultiplexed I/O & Peripheral Pin B (General)
2EI/OMultiplexed I/O & Peripheral Pin E (General)
3CI/OMultiplexed I/O & Peripheral Pin C (General)
4CI/OMultiplexed I/O & Peripheral Pin C (General)
PIN 1 B
I/O
Multiplexed I/O & Peripheral Pin B (General)
Design note: Signal terminal B (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: B. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: JAN2N6383 (MICROCHIP · TO-204AA(TO-3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
JAN2N6383 (TO-204AA(TO-3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
JAN2N6383 (TO-204AA(TO-3)) - 2. Standard Pinout (Top View)
True package pinout (4 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
JAN2N6383 (TO-204AA(TO-3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
JAN2N6383 (TO-204AA(TO-3)) - 4. Package Dimensions (D×E×A)
TO-204AA(TO-3) · 26.70×39.40mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
JAN2N6383 (TO-204AA(TO-3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (4 Pads)Expand ›
6. Application SchematicSCHEMATIC
JAN2N6383 (TO-204AA(TO-3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for JAN2N6383
P1 · p01_fig02EXACT PACKAGE
JAN2N6383 (TO-204AA(TO-3)) — Important: For the latest information, visit our website http://www.microsemi.com.
Important: For the latest information, visit our website http://www.microsemi.com.
P1 · p01_fig012078×2435px
JAN2N6383 (TO-204AA(TO-3)) — T4-LDS-0316, Rev. 1 (9/13/13) ©2013 Microsemi Corporation Page 1 of 7
T4-LDS-0316, Rev. 1 (9/13/13) ©2013 Microsemi Corporation Page 1 of 7
P1 · p01_fig02P1
JAN2N6383 (TO-204AA(TO-3)) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P2 · p02_fig012078×493px
JAN2N6383 (TO-204AA(TO-3)) — PART NOMENCLATURE JAN 2N6283 (e3)
PART NOMENCLATURE JAN 2N6283 (e3)
P2 · p02_fig022078×429px
JAN2N6383 (TO-204AA(TO-3)) — PART NOMENCLATURE JAN 2N6283 (e3) | Reliability Level JAN = JAN Level JANTX = JANTX Level JANTXV = JANTXV Level | Blank = Commercial | JEDEC type number (see Electrical Characteristics | table) | RoHS Compliance e3 = RoHS compliant (availab
PART NOMENCLATURE JAN 2N6283 (e3) | Reliability Level JAN = JAN Level JANTX = JANTX Level JANTXV = JANTXV Level | Blank = Commercial | JEDEC type number (see Electrical Characteristics | table) | RoHS Compliance e3 = RoHS compliant (availab
P5 · p05_fig01911×987px
JAN2N6383 (TO-204AA(TO-3)) — FIGURE 1 Maximum Safe Operating Graph (continuous dc)
FIGURE 1 Maximum Safe Operating Graph (continuous dc)
P5 · p05_fig02846×816px
JAN2N6383 (TO-204AA(TO-3)) — FIGURE 1 Maximum Safe Operating Graph (continuous dc)
FIGURE 1 Maximum Safe Operating Graph (continuous dc)
P6 · p06_fig01911×1146px
JAN2N6383 (TO-204AA(TO-3)) — PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
P6 · p06_fig01P6
JAN2N6383 (TO-204AA(TO-3)) — Datasheet Page 6 (p06_fig01)
Datasheet Page 6 (p06_fig01)

Technical Specifications & Part Details (JAN2N6383)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:JAN2N6383 (TO-204AA(TO-3)) is a 4-pin standard electronic & interconnect component featuring a 39.40 × 26.70 × 8.50 mm mechanical envelope (lead pitch e = 0.00 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
1.0 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
39.40 × 26.70 × 8.50 mm (A1=0.02 mm)
Package family: OTHER (TO-204AA(TO-3))
Pin Count & Lead PitchN / e
4 Pins
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol4 auto-grouped pins
OK
IPC-7351B Land Pattern4 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 13.38×36.41mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TO-204AA(TO-3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
39.40 × 26.70 mm
Height (A) & Pitch (e)IPC-7351B
A=8.50mm · e=0.50mm
Pad Size (W × L)Level B
0.40 × 0.90 mm
Pins / Total PadsTopology
4P / 4Pad (CUSTOM_ARRAY)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TO-204AA(TO-3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — JAN2N6383 (TO-204AA(TO-3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of JAN2N6383 (TO-204AA(TO-3))?

Manufactured by MICROCHIP, the JAN2N6383 is housed in a TO-204AA(TO-3) package with 4 pins and a 0.50 mm lead pitch. Key pins include: 1 (B: Multiplexed I/O & Peripheral Pin B (General)), 2 (E: Multiplexed I/O & Peripheral Pin E (General)), 3 (C: Multiplexed I/O & Peripheral Pin C (General)), 4 (C: Multiplexed I/O & Peripheral Pin C (General)).

What are the IPC-7351B PCB Footprint dimensions for JAN2N6383?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), JAN2N6383 (TO-204AA(TO-3)) has a nominal body envelope of 26.70 × 39.40 mm, pitch e = 0.50 mm, and 4 copper pads plus a central exposed thermal pad (EPAD) of 13.38 × 36.41 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for JAN2N6383?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for JAN2N6383 (MICROCHIP, TO-204AA(TO-3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (4 pins) & JAN2N6383 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1BDigital_IOSignal terminal B (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: B. Supported peripheral buses: General.
2EDigital_IOSignal terminal E (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: E. Supported peripheral buses: General.
3CDigital_IOSignal terminal C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: C. Supported peripheral buses: General.
4CDigital_IOSignal terminal C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: C. Supported peripheral buses: General.
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