SO-8 · 8P
Synchronized Pinout (Symbol / 2D / 3D) (20/20)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (SPI, I2C) |
| 2 | PB9 | I/O | Multiplexed I/O & Peripheral Pin PB9 (SPI) |
| 3 | 3V3 | Power | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | VDD/VDDA | Power | Power Supply Input (VDD/VDDA — 3.3V VDD (Max 4.0V)) |
| 5 | VSS/VSSA | GND | Ground Reference Pin (VSS/VSSA) |
| 6 | PF2NRST - | I/O | Multiplexed I/O & Peripheral Pin PF2NRST - (RTC/CLK) |
| 7 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (SPI, ADC) |
| 8 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (UART, SPI, ADC, PWM) |
| 9 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (UART, SPI, ADC) |
| 10 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (SPI, ADC, PWM) |
| 11 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (SPI, ADC, RTC/CLK) |
| 12 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM) |
| 13 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM) |
| 14 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM) |
| 15 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (SPI, RTC/CLK) |
| 16 | PA11[PA9] | I/O | Multiplexed I/O & Peripheral Pin PA11[PA9] (UART, SPI, ADC) |
| 17 | PA12[PA10] | I/O | Multiplexed I/O & Peripheral Pin PA12[PA10] (UART, SPI, I2C, ADC) |
| 18 | PA13 | I/O | Multiplexed I/O & Peripheral Pin PA13 (ADC, SWD/JTAG) |
| 19 | PA15 | I/O | Multiplexed I/O & Peripheral Pin PA15 (UART, SPI) |
| 20 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (UART) |
PIN 1 PB8
I/OMultiplexed I/O & Peripheral Pin PB8 (SPI, I2C)
Design note: Alt: SPI2_SCKTIM16CH1 ,_ , I2C1_SCLEVENTOUT ,
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 32 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
TSSOP-20 · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (32 figures · Page 1/3)
Showing 1–12 of 32 uncropped original figures for STM32G031 / STM32C031
P34 · p34_fig01EXACT PACKAGE
P34 · p34_fig02EXACT PACKAGE
P106 · p106_fig01EXACT PACKAGE
P1 · p01_fig011241×701px
P32 · p32_fig011546×917px
P32 · p32_fig021546×903px
P32 · p32_fig03517×517px
P33 · p33_fig011546×776px
P33 · p33_fig021546×826px
P33 · p33_fig03390×390px
P34 · p34_fig031546×858px
P44 · p44_fig011546×1316px
Page 1 / 3 (32 extracted figures)
Technical Specifications & Part Details (STM32G031F4P6TR)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32G031F4P6TR (TSSOP-20) is a 20-pin embedded microcontroller unit (mcu) featuring a 6.50 × 4.40 × 1.20 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.62 V - 3.6 V supply operation across -40°C to 85°C with integrated UART, SPI, I2C, I2S, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.62 V - 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
64 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
17 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.20 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol20 auto-grouped pins
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32G031 / STM32C031 (20)
SO-8 · 8P
SO-8 · 8P
SOP-8 · 8P
SOP-8 · 8P
TSSOP-20 · 20P
IPC-7351B
20P6.5×4.4×1.20mmP=0.65mm
STM32G031 / STM32C031 (TSSOP-20)
TSSOP-20 · 20P
IPC-7351B
20P6.5×4.4×1.20mmP=0.65mm
STM32G031 / STM32C031 (TSSOP-20)
TSSOP-20 · 20P
TSSOP-20 · 20P
TSSOP-20 · 20P
UFQFPN-28(4x4) · 28P
IPC-7351B
28P4.0×4.0×0.55mmP=0.5mm
STM32G031 / STM32C031 (UFQFPN-28(4x4))
UFQFPN-28(4x4) · 28P
IPC-7351B
28P4.0×4.0×0.60mmP=0.5mm
STM32G031 / STM32C031 (UFQFPN-28(4x4))
UFQFPN-28(4x4) · 28P
IPC-7351B
28P4.0×4.0×0.55mmP=0.5mm
STM32G031 / STM32C031 (UFQFPN-28(4x4))
UFQFPN-28(4x4) · 28P
IPC-7351B
28P4.0×4.0×0.55mmP=0.5mm
STM32G031 / STM32C031 (UFQFPN-28(4x4))
UFQFPN-28(4x4) · 28P
IPC-7351B
28P4.0×4.0×0.55mmP=0.5mm
STM32G031 / STM32C031 (UFQFPN-28(4x4))
UFQFPN-28(4x4) · 28P
IPC-7351B
28P4.0×4.0×0.55mmP=0.5mm
STM32G031 / STM32C031 (UFQFPN-28(4x4))
UFQFPN-28(4x4) · 28P
IPC-7351B
28P4.0×4.0×0.55mmP=0.5mm
STM32G031 / STM32C031 (UFQFPN-28(4x4))
UFQFPN-28(4x4) · 28P
IPC-7351B
28P4.0×4.0×0.55mmP=0.5mm
STM32G031 / STM32C031 (UFQFPN-28(4x4))
UFQFPN-28(4x4) · 28P
IPC-7351B
28P4.0×4.0×0.60mmP=0.5mm
STM32G031 / STM32C031 (UFQFPN-28(4x4))
UFQFPN-28(4x4) · 28P
IPC-7351B
28P4.0×4.0×0.55mmP=0.5mm
STM32G031 / STM32C031 (UFQFPN-28(4x4))
Mechanical Dimensions & Land Pattern (TSSOP-20)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit TSSOP-20 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32G031F4P6TR (TSSOP-20)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32G031F4P6TR (TSSOP-20)?
Manufactured by ST, the STM32G031F4P6TR is housed in a TSSOP-20 package with 20 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 1.62 V - 3.6 V. Key pins include: 1 (PB8: Multiplexed I/O & Peripheral Pin PB8 (SPI, I2C)), 2 (PB9: Multiplexed I/O & Peripheral Pin PB9 (SPI)), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (VDD/VDDA: Power Supply Input (VDD/VDDA — 3.3V VDD (Max 4.0V))), 5 (VSS/VSSA: Ground Reference Pin (VSS/VSSA)), 6 (PF2NRST -: Multiplexed I/O & Peripheral Pin PF2NRST - (RTC/CLK)).
What are the IPC-7351B PCB Footprint dimensions for STM32G031F4P6TR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32G031F4P6TR (TSSOP-20) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32G031F4P6TR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32G031F4P6TR (ST, TSSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (20 pins) & STM32G031 / STM32C031 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKTIM16CH1, I2C1_SCLEVENTOUT. Supported peripheral buses: SPI, I2C. |
| 2 | PB9 | Digital_IO | Signal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSI2C1SDA. Supported peripheral buses: SPI. |
| 3 | 3V3 | Power_In | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | VDD/VDDA | Power_In | Primary positive power supply input (VDD/VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 5 | VSS/VSSA | GND | 0V electrical ground return terminal (VSS/VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| 6 | PF2NRST - | Digital_IO | Signal terminal PF2NRST - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2NRST -. Supported peripheral buses: RTC/CLK. |
| 7 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKUSART2CTS. Supported peripheral buses: SPI, ADC. |
| 8 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 9 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI, ADC. |
| 10 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOUSART2RX. Supported peripheral buses: SPI, ADC, PWM. |
| 11 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI2_MOSITIM14CH1. Supported peripheral buses: SPI, ADC, RTC/CLK. |
| 12 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, PWM. |
| 13 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC, PWM. |
| 14 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM. |
| 15 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI, RTC/CLK. |
| 16 | PA11[PA9] | Digital_IO | Signal terminal PA11[PA9] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC. |
| 17 | PA12[PA10] | Digital_IO | Signal terminal PA12[PA10] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, I2C2_SDA. Supported peripheral buses: UART, SPI, I2C, ADC. |
| 18 | PA13 | Digital_IO | Signal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: ADC, SWD/JTAG. |
| 19 | PA15 | Digital_IO | Signal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI. |
| 20 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART. |