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RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) — Symbol, Footprint IPC-7351B & 3D STEP Model

RN42APL-I/RM550

MICROCHIPID: C639025WIRELM-SMD_MICROCHIP_RN42 · 36 Pins · Pitch 1.00mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42)1GND2SPI_MOSI3GPIO64GPIO75RESET6SPI_CLK7PCM_CLK8PCM_SYNC9PCM_IN10PCM_OUT11VDD12GND13UART_RX14UART_TX15UART_RTS16UART_CTS17USB D+_18USB D-_39EP38EP37EP36EP35AIO134GPIO1133GPIO1032GPIO931GPIO830AIO029GND28GND24SPI_MISO23SPI_CSB22GPIO421GPIO520GPIO319GPIO2Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
ANTENNA KEEPOUT (5.3mm)123456789101112131415161718192021222324302831323334293536373938E=13.40mm · Pitch e=1.00mmD=25.80mm-15-13-11-9-7-5-3-11357911131520181614121086420-2-4-6-8-10-12-14-16-18-20mm
3. 3D CAD MODEL
Package Body: 13.40mm × 25.80mm · Pitch: 1.00mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (36/36)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GNDGNDGround Reference Pin (GND)
2SPI_MOSII/OMultiplexed I/O & Peripheral Pin SPI_MOSI (SPI)
3GPIO6I/OMultiplexed I/O & Peripheral Pin GPIO6 (General)
4GPIO7I/OMultiplexed I/O & Peripheral Pin GPIO7 (General)
5RESETISystem Enable & Hardware Reset (RESET)
6SPI_CLKI/OMultiplexed I/O & Peripheral Pin SPI_CLK (SPI)
7PCM_CLKI/OMultiplexed I/O & Peripheral Pin PCM_CLK (General)
8PCM_SYNCI/OMultiplexed I/O & Peripheral Pin PCM_SYNC (General)
9PCM_INI/OMultiplexed I/O & Peripheral Pin PCM_IN (General)
10PCM_OUTI/OMultiplexed I/O & Peripheral Pin PCM_OUT (General)
11VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
12GNDGNDGround Reference Pin (GND)
13UART_RXI/OMultiplexed I/O & Peripheral Pin UART_RX (UART)
14UART_TXI/OMultiplexed I/O & Peripheral Pin UART_TX (UART)
15UART_RTSI/OMultiplexed I/O & Peripheral Pin UART_RTS (UART)
16UART_CTSI/OMultiplexed I/O & Peripheral Pin UART_CTS (UART)
17USB D+_I/OMultiplexed I/O & Peripheral Pin USB D+_ (USB)
18USB D-_I/OMultiplexed I/O & Peripheral Pin USB D-_ (USB)
19GPIO2I/OMultiplexed I/O & Peripheral Pin GPIO2 (General)
20GPIO3I/OMultiplexed I/O & Peripheral Pin GPIO3 (General)
21GPIO5I/OMultiplexed I/O & Peripheral Pin GPIO5 (General)
22GPIO4I/OMultiplexed I/O & Peripheral Pin GPIO4 (General)
23SPI_CSBI/OMultiplexed I/O & Peripheral Pin SPI_CSB (SPI)
24SPI_MISOI/OMultiplexed I/O & Peripheral Pin SPI_MISO (SPI)
28GNDGNDGround Reference Pin (GND)
29GNDGNDGround Reference Pin (GND)
30AIO0I/OMultiplexed I/O & Peripheral Pin AIO0 (General)
31GPIO8I/OMultiplexed I/O & Peripheral Pin GPIO8 (UART)
32GPIO9I/OMultiplexed I/O & Peripheral Pin GPIO9 (General)
33GPIO10I/OMultiplexed I/O & Peripheral Pin GPIO10 (General)
34GPIO11I/OMultiplexed I/O & Peripheral Pin GPIO11 (General)
35AIO1I/OMultiplexed I/O & Peripheral Pin AIO1 (General)
36EPGNDExposed Thermal & Ground Pad (EP)
37EPGNDExposed Thermal & Ground Pad (EP)
38EPGNDExposed Thermal & Ground Pad (EP)
39EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 GND
GND
Ground Reference Pin (GND)
Design note: Groundreference
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 20 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: RN42APL-I/RM550 (MICROCHIP · WIRELM-SMD_MICROCHIP_RN42)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) - 2. Standard Pinout (Top View)
True package pinout (36 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) - 4. Package Dimensions (D×E×A)
WIRELM-SMD_MICROCHIP_RN42 · 13.40×25.80mm · Pitch 1.00mmExpand ›
5. Recommended Land PatternLAND PATTERN
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) - 5. Recommended Land Pattern
IPC-7351B Footprint (36 Pads)Expand ›
6. Application SchematicSCHEMATIC
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (20 figures · Page 1/2)
Showing 1–12 of 20 uncropped original figures for RN42 / RN42APL / RN42HID
P1 · p01_fig01376×200px
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) — Class 2 Bluetooth® Module with EDR Support
Class 2 Bluetooth® Module with EDR Support
P1 · p01_fig02643×683px
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) — Class 2 Bluetooth® Module with EDR Support
Class 2 Bluetooth® Module with EDR Support
P1 · p01_fig02P1
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P2 · p02_fig011779×654px
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) — TO OUR VALUED CUSTOMERS
TO OUR VALUED CUSTOMERS
P5 · p05_fig01867×1063px
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) — FIGURE 1-4: RN42 PIN DIAGRAM
FIGURE 1-4: RN42 PIN DIAGRAM
P5 · p05_fig02867×1104px
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) — FIGURE 1-4: RN42 PIN DIAGRAM
FIGURE 1-4: RN42 PIN DIAGRAM
P5 · p05_fig03871×1077px
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) — FIGURE 1-5: RN42N PIN DIAGRAM
FIGURE 1-5: RN42N PIN DIAGRAM
P5 · p05_fig04867×1105px
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) — FIGURE 1-5: RN42N PIN DIAGRAM
FIGURE 1-5: RN42N PIN DIAGRAM
P5 · p05_fig02P5
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) — Datasheet Page 5 (p05_fig02)
Datasheet Page 5 (p05_fig02)
P5 · p05_fig03P5
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) — Datasheet Page 5 (p05_fig03)
Datasheet Page 5 (p05_fig03)
P7 · p07_fig011778×1457px
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) — FIGURE 2-1: RN42 RECOMMENDED PCB FOOTPRINT
FIGURE 2-1: RN42 RECOMMENDED PCB FOOTPRINT
P7 · p07_fig01P7
RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) — Datasheet Page 7 (p07_fig01)
Datasheet Page 7 (p07_fig01)
Page 1 / 2 (20 extracted figures)

Technical Specifications & Part Details (RN42APL-I/RM550)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) is a 36-pin wireless wi-fi / bluetooth le soc module featuring a 25.80 × 13.40 × 2.40 mm mechanical envelope (lead pitch e = 1.00 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, UART, SPI interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
25.80 × 13.40 × 2.40 mm (A1=0.00 mm)
Package family: CASTELLATED_MODULE (WIRELM-SMD_MICROCHIP_RN42)
Pin Count & Lead PitchN / e
36 Pins | Pitch e = 1.00 mm (39.4 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, UART, SPI
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol36 auto-grouped pins
OK
IPC-7351B Land Pattern36 pads · Pitch 1.00mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WIRELM-SMD_MICROCHIP_RN42)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
25.80 × 13.40 mm
Height (A) & Pitch (e)IPC-7351B
A=2.40mm · e=1.00mm
Pad Size (W × L)Level B
0.80 × 2.00 mm
Pins / Total PadsTopology
36P / 36Pad (CASTELLATED_MODULE)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WIRELM-SMD_MICROCHIP_RN42
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42)?

Manufactured by MICROCHIP, the RN42APL-I/RM550 is housed in a WIRELM-SMD_MICROCHIP_RN42 package with 36 pins and a 1.00 mm lead pitch. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (SPI_MOSI: Multiplexed I/O & Peripheral Pin SPI_MOSI (SPI)), 3 (GPIO6: Multiplexed I/O & Peripheral Pin GPIO6 (General)), 4 (GPIO7: Multiplexed I/O & Peripheral Pin GPIO7 (General)), 5 (RESET: System Enable & Hardware Reset (RESET)), 6 (SPI_CLK: Multiplexed I/O & Peripheral Pin SPI_CLK (SPI)).

What are the IPC-7351B PCB Footprint dimensions for RN42APL-I/RM550?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), RN42APL-I/RM550 (WIRELM-SMD_MICROCHIP_RN42) has a nominal body envelope of 13.40 × 25.80 mm, pitch e = 1.00 mm, and 36 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for RN42APL-I/RM550?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for RN42APL-I/RM550 (MICROCHIP, WIRELM-SMD_MICROCHIP_RN42) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (36 pins) & RN42 / RN42APL / RN42HID Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
2SPI_MOSIDigital_IOSignal terminal SPI_MOSI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI.
3GPIO6Digital_IOSignal terminal GPIO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO6. Supported peripheral buses: General.
4GPIO7Digital_IOSignal terminal GPIO7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO7. Supported peripheral buses: General.
5RESETDigital_IOActive-low hardware reset terminal (RESET): pulling this pin Low resets the processor core and peripherals.
6SPI_CLKDigital_IOSignal terminal SPI_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPIINTERFACE. Supported peripheral buses: SPI.
7PCM_CLKDigital_IOSignal terminal PCM_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PCM_CLK. Supported peripheral buses: General.
8PCM_SYNCDigital_IOSignal terminal PCM_SYNC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PCM_SYNC. Supported peripheral buses: General.
9PCM_INDigital_IOSignal terminal PCM_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PCM_IN. Supported peripheral buses: General.
10PCM_OUTDigital_IOSignal terminal PCM_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PCM_OUT. Supported peripheral buses: General.
11VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
12GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
13UART_RXDigital_IOSignal terminal UART_RX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UART_RX. Supported peripheral buses: UART.
14UART_TXDigital_IOSignal terminal UART_TX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UART_TX. Supported peripheral buses: UART.
15UART_RTSDigital_IOSignal terminal UART_RTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UART_RTS. Supported peripheral buses: UART.
16UART_CTSDigital_IOSignal terminal UART_CTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UART_CTS. Supported peripheral buses: UART.
17USB D+_Digital_IOSignal terminal USB D+_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB D+_. Supported peripheral buses: USB.
18USB D-_Digital_IOSignal terminal USB D-_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB D-_. Supported peripheral buses: USB.
19GPIO2Digital_IOSignal terminal GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General.
20GPIO3Digital_IOSignal terminal GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General.
21GPIO5Digital_IOSignal terminal GPIO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO5. Supported peripheral buses: General.
22GPIO4Digital_IOSignal terminal GPIO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO4. Supported peripheral buses: General.
23SPI_CSBDigital_IOSignal terminal SPI_CSB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPIINTERFACE. Supported peripheral buses: SPI.
24SPI_MISODigital_IOSignal terminal SPI_MISO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPIINTERFACE. Supported peripheral buses: SPI.
28GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
29GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
30AIO0Digital_IOSignal terminal AIO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AIO0. Supported peripheral buses: General.
31GPIO8Digital_IOSignal terminal GPIO8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO8. Supported peripheral buses: UART.
32GPIO9Digital_IOSignal terminal GPIO9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO9. Supported peripheral buses: General.
33GPIO10Digital_IOSignal terminal GPIO10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO10. Supported peripheral buses: General.
34GPIO11Digital_IOSignal terminal GPIO11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO11. Supported peripheral buses: General.
35AIO1Digital_IOSignal terminal AIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AIO1. Supported peripheral buses: General.
36EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
37EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
38EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
39EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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