QFN-32-EP(5x5) · 33P
33P5.0×5.0×0.85mmP=0.5mm
KSZ8061 (QFN-32-EP(5x5))
Synchronized Pinout (Symbol / 2D / 3D) (49/49)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | XI | I/O | Multiplexed I/O & Peripheral Pin XI (RTC/CLK) |
| 2 | XO | I/O | Multiplexed I/O & Peripheral Pin XO (RTC/CLK) |
| 3 | AVDDH | Power | Power Supply Input (AVDDH — 3.3V / 5.0V Standard Logic) |
| 4 | TXP | I/O | Multiplexed I/O & Peripheral Pin TXP (General) |
| 5 | TXM | I/O | Multiplexed I/O & Peripheral Pin TXM (General) |
| 6 | RXP | I/O | Multiplexed I/O & Peripheral Pin RXP (General) |
| 7 | RXM | I/O | Multiplexed I/O & Peripheral Pin RXM (General) |
| 8 | AVDDL | Power | Power Supply Input (AVDDL — 3.3V / 5.0V Standard Logic) |
| 9 | VDDL | Power | Power Supply Input (VDDL — 3.3V / 5.0V Standard Logic) |
| 10 | MDIO | I/O | Multiplexed I/O & Peripheral Pin MDIO (General) |
| 11 | MDC | I/O | Multiplexed I/O & Peripheral Pin MDC (General) |
| 12 | RXER/QWF | I/O | Multiplexed I/O & Peripheral Pin RXER/QWF (General) |
| 13 | RXDV/ CONFIG2 | I/O | Multiplexed I/O & Peripheral Pin RXDV/ CONFIG2 (UART) |
| 14 | RXD3/ PHYAD0 | I/O | Multiplexed I/O & Peripheral Pin RXD3/ PHYAD0 (UART) |
| 15 | VDDIO | Power | Power Supply Input (VDDIO — 3.3V / 5.0V Standard Logic) |
| 16 | RXD2/ PHYAD1 | I/O | Multiplexed I/O & Peripheral Pin RXD2/ PHYAD1 (UART) |
| 17 | RXD1/ PHYAD2 | I/O | Multiplexed I/O & Peripheral Pin RXD1/ PHYAD2 (UART) |
| 18 | RXD0/ AUTONEG | I/O | Multiplexed I/O & Peripheral Pin RXD0/ AUTONEG (UART) |
| 19 | RXC/ CONFIG0 | I/O | Multiplexed I/O & Peripheral Pin RXC/ CONFIG0 (General) |
| 20 | TXC | I/O | Multiplexed I/O & Peripheral Pin TXC (General) |
| 21 | TXEN | I/O | Multiplexed I/O & Peripheral Pin TXEN (General) |
| 22 | TXD0 | I/O | Multiplexed I/O & Peripheral Pin TXD0 (UART) |
| 23 | TXD1 | I/O | Multiplexed I/O & Peripheral Pin TXD1 (UART) |
| 24 | LED0 | I/O | Multiplexed I/O & Peripheral Pin LED0 (General) |
| 25 | TXD2 | I/O | Multiplexed I/O & Peripheral Pin TXD2 (UART) |
| 26 | TXD3 | I/O | Multiplexed I/O & Peripheral Pin TXD3 (UART) |
| 27 | CRS/ CONFIG1 | I/O | Multiplexed I/O & Peripheral Pin CRS/ CONFIG1 (General) |
| 28 | RESET# | I | System Enable & Hardware Reset (RESET#) |
| 29 | INTRP/ NAND Tree#_ | I/O | Multiplexed I/O & Peripheral Pin INTRP/ NAND Tree#_ (General) |
| 30 | VDDL | Power | Power Supply Input (VDDL — 3.3V / 5.0V Standard Logic) |
| 31 | REXT | I/O | Multiplexed I/O & Peripheral Pin REXT (General) |
| 32 | SIGDET | I/O | Multiplexed I/O & Peripheral Pin SIGDET (General) |
| 33 | VDDIO | Power | Power Supply Input (VDDIO — 3.3V / 5.0V Standard Logic) |
| 34 | TXER | I/O | Multiplexed I/O & Peripheral Pin TXER (General) |
| 35 | TXD2 | I/O | Multiplexed I/O & Peripheral Pin TXD2 (UART) |
| 36 | GND | GND | Ground Reference Pin (GND) |
| 37 | TXD3 | I/O | Multiplexed I/O & Peripheral Pin TXD3 (UART) |
| 38 | CRS | I/O | Multiplexed I/O & Peripheral Pin CRS (General) |
| 39 | LED0 | I/O | Multiplexed I/O & Peripheral Pin LED0 (General) |
| 40 | LED1 | I/O | Multiplexed I/O & Peripheral Pin LED1 (General) |
| 41 | VDDIO | Power | Power Supply Input (VDDIO — 3.3V / 5.0V Standard Logic) |
| 42 | RESET# | I | System Enable & Hardware Reset (RESET#) |
| 43 | GND | GND | Ground Reference Pin (GND) |
| 44 | INTRP | I/O | Multiplexed I/O & Peripheral Pin INTRP (General) |
| 45 | VDDL | Power | Power Supply Input (VDDL — 3.3V / 5.0V Standard Logic) |
| 46 | GND | GND | Ground Reference Pin (GND) |
| 47 | REXT | I/O | Multiplexed I/O & Peripheral Pin REXT (General) |
| 48 | SIGDET | I/O | Multiplexed I/O & Peripheral Pin SIGDET (General) |
| 49 | GND | GND | Exposed Thermal & Ground Pad (GND) |
PIN 1 XI
I/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
Design note: Crystal/Oscillator/ExternalClockInput 25MHz±50ppm ThisinputreferencestheAVDDHpowersupply . .
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
TQFN-48-EP(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for KSZ8061
P1 · p01_fig01376×200px
P5 · p05_fig01914×953px
P5 · p05_fig01P5
P29 · p29_fig011421×781px
P29 · p29_fig021379×828px
P29 · p29_fig02P29
P58 · p58_fig01All Packages in PDF
P59 · p59_fig01All Packages in PDF
Technical Specifications & Part Details (KSZ8061MNGW)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:KSZ8061MNGW (TQFN-48-EP(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (TQFN-48-EP(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol49 auto-grouped pins
IPC-7351B Land Pattern49 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteEPAD 3.50×3.50mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — KSZ8061 (2)
TQFN-48-EP(7x7) · 49P
49P7.0×7.0×0.85mmP=0.5mm
KSZ8061 (TQFN-48-EP(7x7))
Mechanical Dimensions & Land Pattern (TQFN-48-EP(7x7))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.85 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit TQFN-48-EP(7x7) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — KSZ8061MNGW (TQFN-48-EP(7x7))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of KSZ8061MNGW (TQFN-48-EP(7x7))?
Manufactured by MICROCHIP, the KSZ8061MNGW is housed in a TQFN-48-EP(7x7) package with 49 pins and a 0.50 mm lead pitch. Key pins include: 1 (XI: Multiplexed I/O & Peripheral Pin XI (RTC/CLK)), 2 (XO: Multiplexed I/O & Peripheral Pin XO (RTC/CLK)), 3 (AVDDH: Power Supply Input (AVDDH — 3.3V / 5.0V Standard Logic)), 4 (TXP: Multiplexed I/O & Peripheral Pin TXP (General)), 5 (TXM: Multiplexed I/O & Peripheral Pin TXM (General)), 6 (RXP: Multiplexed I/O & Peripheral Pin RXP (General)).
What are the IPC-7351B PCB Footprint dimensions for KSZ8061MNGW?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), KSZ8061MNGW (TQFN-48-EP(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 3.50 × 3.50 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for KSZ8061MNGW?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for KSZ8061MNGW (MICROCHIP, TQFN-48-EP(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (49 pins) & KSZ8061 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | XI | Digital_IO | Signal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK. |
| 2 | XO | Digital_IO | Signal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK. |
| 3 | AVDDH | Power_In | Primary positive power supply input (AVDDH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 4 | TXP | Digital_IO | Signal terminal TXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXP. Supported peripheral buses: General. |
| 5 | TXM | Digital_IO | Signal terminal TXM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXM. Supported peripheral buses: General. |
| 6 | RXP | Digital_IO | Signal terminal RXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXP. Supported peripheral buses: General. |
| 7 | RXM | Digital_IO | Signal terminal RXM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXM. Supported peripheral buses: General. |
| 8 | AVDDL | Power_In | Primary positive power supply input (AVDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 9 | VDDL | Power_In | Primary positive power supply input (VDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 10 | MDIO | Open_Drain | Signal terminal MDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIO. Supported peripheral buses: General. |
| 11 | MDC | Digital_IO | Signal terminal MDC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDC. Supported peripheral buses: General. |
| 12 | RXER/QWF | Digital_IO | Signal terminal RXER/QWF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXER/QWF. Supported peripheral buses: General. |
| 13 | RXDV/ CONFIG2 | Digital_IO | Signal terminal RXDV/ CONFIG2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXDV/ CONFIG2. Supported peripheral buses: UART. |
| 14 | RXD3/ PHYAD0 | Digital_IO | Signal terminal RXD3/ PHYAD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3/ PHYAD0. Supported peripheral buses: UART. |
| 15 | VDDIO | Power_In | Primary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 16 | RXD2/ PHYAD1 | Digital_IO | Signal terminal RXD2/ PHYAD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2/ PHYAD1. Supported peripheral buses: UART. |
| 17 | RXD1/ PHYAD2 | Digital_IO | Signal terminal RXD1/ PHYAD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1/ PHYAD2. Supported peripheral buses: UART. |
| 18 | RXD0/ AUTONEG | Digital_IO | Signal terminal RXD0/ AUTONEG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0/ AUTONEG. Supported peripheral buses: UART. |
| 19 | RXC/ CONFIG0 | Digital_IO | Signal terminal RXC/ CONFIG0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXC/ CONFIG0. Supported peripheral buses: General. |
| 20 | TXC | Digital_IO | Signal terminal TXC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXC. Supported peripheral buses: General. |
| 21 | TXEN | Digital_IO | Signal terminal TXEN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXEN. Supported peripheral buses: General. |
| 22 | TXD0 | Digital_IO | Signal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART. |
| 23 | TXD1 | Digital_IO | Signal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART. |
| 24 | LED0 | Digital_IO | Signal terminal LED0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED0. Supported peripheral buses: General. |
| 25 | TXD2 | Digital_IO | Signal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART. |
| 26 | TXD3 | Digital_IO | Signal terminal TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART. |
| 27 | CRS/ CONFIG1 | Digital_IO | Signal terminal CRS/ CONFIG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CRS/ CONFIG1. Supported peripheral buses: General. |
| 28 | RESET# | Digital_IO | Active-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals. |
| 29 | INTRP/ NAND Tree#_ | Open_Drain | Signal terminal INTRP/ NAND Tree#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INTRP/ NAND Tree#_. Supported peripheral buses: General. |
| 30 | VDDL | Power_In | Primary positive power supply input (VDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 31 | REXT | Digital_IO | Signal terminal REXT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: REXT. Supported peripheral buses: General. |
| 32 | SIGDET | Digital_IO | Signal terminal SIGDET (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SIGDET. Supported peripheral buses: General. |
| 33 | VDDIO | Power_In | Primary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 34 | TXER | Digital_IO | Signal terminal TXER (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXER. Supported peripheral buses: General. |
| 35 | TXD2 | Digital_IO | Signal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART. |
| 36 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 37 | TXD3 | Digital_IO | Signal terminal TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART. |
| 38 | CRS | Digital_IO | Signal terminal CRS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CRS. Supported peripheral buses: General. |
| 39 | LED0 | Digital_IO | Signal terminal LED0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED0. Supported peripheral buses: General. |
| 40 | LED1 | Digital_IO | Signal terminal LED1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED1. Supported peripheral buses: General. |
| 41 | VDDIO | Power_In | Primary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 42 | RESET# | Digital_IO | Active-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals. |
| 43 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 44 | INTRP | Digital_IO | Signal terminal INTRP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INTRP. Supported peripheral buses: General. |
| 45 | VDDL | Power_In | Primary positive power supply input (VDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 46 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 47 | REXT | Digital_IO | Signal terminal REXT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: REXT. Supported peripheral buses: General. |
| 48 | SIGDET | Digital_IO | Signal terminal SIGDET (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SIGDET. Supported peripheral buses: General. |
| 49 | GND | GND | Bottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |