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SCH3224-SY (WFBGA-100) — Symbol, Footprint IPC-7351B & 3D STEP Model

SCH3224-SY

MICROCHIPID: C633441WFBGA-100 · 100 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · SCH3224-SY (WFBGA-100)A2REMOTE2 -A3HVSSA4PWM1A5nHWM_INTA6PWM3A7PWRGD_OUTA8GP62 / nCTS4A9GP66 / nDSR4A10VSSB1REMOTE1 -B2+25V IN ._B3HVTRB4FANTACH3B5PWM2B6nTHERMTRIPB7PWRGD_PSB8GP67 / nRTS4B9GP65 / TXD4B10nRSMRSTB11CLKI32C1+5V_INC2+12V_INC3GP40 / DRVDEC4FANTACH1C5FANTACH2C6VSSC7GP34 / nDTR4C8GP64 / RXD4C9GP63 / nDCD4C10GP31 / nRI4C11GP12 / nDCD3D1LAD2D2VSSD3VTRD9GP61 / nLED2D10GP60 / nLED1D11GP13 / nRI3E1LFRAME#E2LAD1E3CLOCKIE5RESERVED VSSE6nHWM_INTE7nFPRST / GP3E9GP14 / nDSR3E10VTRE11GP15 / nDTR3F1PCI RESET#_F2LAD3F3LAD0F5RESERVED VSSL10GP55 / nRTS2L9VTRL8STRAPOPT ( VL7VSSL6nDCD1L5GP37 / A20ML4GP36 / nKBDRL3MDAT / GP32L2KCLK / GP22K11PS ON#_K10GP56 / nCTS2K9GP51 / nDCD2K8RXD1K7nRI1K6nDSR1K5nRTS1 / SYSOK4MCLK / GP33K3GP27 / nIO SK2nPCIRST2 / GK1VBATJ11PB IN#_J10GP57 / nDTR2J9GP52 / RXD2(J8TXD1 / SIOXNJ7nCTS1J6nDTR1 / SYSOJ5GP50 / nRI2J4KDAT / GP21J3nPCIRST3 / GJ2nPCIRST1 / GJ1AVSSH11SLP SX#_H10PB OUT#_H9GP53 / TXD2(H3nIDE RSTDRV H2VCCH1VSSG11GP16 / nCTS3G10GP11 / TXD3G9GP54 / nDSR2G7VSSG6VTRG5TEST VSSb =G3LDRQ#G2SER_IRQG1PCI_CLKF11GP42 / nIO_PF10GP17 / nRTS3F9GP10 / RXD3F7VTRGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
K11J11H11G11F11E11D11C11B11L10K10J10H10G10F10E10D10C10B10A10L9K9J9H9G9F9E9D9C9B9A9L8K8J8C8B8A8L7K7J7G7F7E7C7B7A7L6K6J6G6E6C6B6A6L5K5J5G5F5E5C5B5A5L4K4J4C4B4A4L3K3J3H3G3F3E3D3C3B3A3L2K2J2H2G2F2E2D2C2B2A2K1J1H1G1F1E1D1C1B1E=8.00mm · Pitch e=0.65mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A2REMOTE2 -I/OMultiplexed I/O & Peripheral Pin REMOTE2 - (General)
A3HVSSGNDGround Reference Pin (HVSS)
A4PWM1I/OMultiplexed I/O & Peripheral Pin PWM1 (PWM)
A5nHWM_INTI/OMultiplexed I/O & Peripheral Pin nHWM_INT (General)
A6PWM3I/OMultiplexed I/O & Peripheral Pin PWM3 (PWM)
A7PWRGD_OUTI/OMultiplexed I/O & Peripheral Pin PWRGD_OUT (General)
A8GP62 / nCTS4I/OMultiplexed I/O & Peripheral Pin GP62 / nCTS4 (General)
A9GP66 / nDSR4I/OMultiplexed I/O & Peripheral Pin GP66 / nDSR4 (General)
A10VSSGNDGround Reference Pin (VSS)
B1REMOTE1 -I/OMultiplexed I/O & Peripheral Pin REMOTE1 - (General)
B2+25V IN ._PowerPower Supply Input (+25V IN ._ — 3.3V / 5.0V Standard Logic)
B3HVTRI/OMultiplexed I/O & Peripheral Pin HVTR (General)
B4FANTACH3I/OMultiplexed I/O & Peripheral Pin FANTACH3 (General)
B5PWM2I/OMultiplexed I/O & Peripheral Pin PWM2 (PWM)
B6nTHERMTRIPI/OMultiplexed I/O & Peripheral Pin nTHERMTRIP (General)
B7PWRGD_PSI/OMultiplexed I/O & Peripheral Pin PWRGD_PS (General)
B8GP67 / nRTS4I/OMultiplexed I/O & Peripheral Pin GP67 / nRTS4 (General)
B9GP65 / TXD4I/OMultiplexed I/O & Peripheral Pin GP65 / TXD4 (UART)
B10nRSMRSTI/OMultiplexed I/O & Peripheral Pin nRSMRST (General)
B11CLKI32I/OMultiplexed I/O & Peripheral Pin CLKI32 (General)
C1+5V_INPowerPower Supply Input (+5V_IN — 3.3V / 5.0V Standard Logic)
C2+12V_INI/OMultiplexed I/O & Peripheral Pin +12V_IN (General)
C3GP40 / DRVDEN0(out)I/OMultiplexed I/O & Peripheral Pin GP40 / DRVDEN0(out) (General)
C4FANTACH1I/OMultiplexed I/O & Peripheral Pin FANTACH1 (General)
C5FANTACH2I/OMultiplexed I/O & Peripheral Pin FANTACH2 (General)
C6VSSGNDGround Reference Pin (VSS)
C7GP34 / nDTR4I/OMultiplexed I/O & Peripheral Pin GP34 / nDTR4 (General)
C8GP64 / RXD4I/OMultiplexed I/O & Peripheral Pin GP64 / RXD4 (UART)
C9GP63 / nDCD4I/OMultiplexed I/O & Peripheral Pin GP63 / nDCD4 (General)
C10GP31 / nRI4I/OMultiplexed I/O & Peripheral Pin GP31 / nRI4 (General)
C11GP12 / nDCD3I/OMultiplexed I/O & Peripheral Pin GP12 / nDCD3 (General)
D1LAD2I/OMultiplexed I/O & Peripheral Pin LAD2 (General)
D2VSSGNDGround Reference Pin (VSS)
D3VTRI/OMultiplexed I/O & Peripheral Pin VTR (General)
D9GP61 / nLED2 / CLKOI/OMultiplexed I/O & Peripheral Pin GP61 / nLED2 / CLKO (General)
D10GP60 / nLED1 / WDTI/OMultiplexed I/O & Peripheral Pin GP60 / nLED1 / WDT (General)
D11GP13 / nRI3I/OMultiplexed I/O & Peripheral Pin GP13 / nRI3 (General)
E1LFRAME#I/OMultiplexed I/O & Peripheral Pin LFRAME# (General)
E2LAD1I/OMultiplexed I/O & Peripheral Pin LAD1 (General)
E3CLOCKII/OMultiplexed I/O & Peripheral Pin CLOCKI (General)
E5RESERVED VSSc =GNDGround Reference Pin (RESERVED VSSc =)
E6nHWM_INTI/OMultiplexed I/O & Peripheral Pin nHWM_INT (General)
E7nFPRST / GP30I/OMultiplexed I/O & Peripheral Pin nFPRST / GP30 (General)
E9GP14 / nDSR3I/OMultiplexed I/O & Peripheral Pin GP14 / nDSR3 (General)
E10VTRI/OMultiplexed I/O & Peripheral Pin VTR (General)
E11GP15 / nDTR3I/OMultiplexed I/O & Peripheral Pin GP15 / nDTR3 (General)
F1PCI RESET#_ISystem Enable & Hardware Reset (PCI RESET#_)
F2LAD3I/OMultiplexed I/O & Peripheral Pin LAD3 (General)
F3LAD0I/OMultiplexed I/O & Peripheral Pin LAD0 (General)
F5RESERVED VSSc =GNDGround Reference Pin (RESERVED VSSc =)
F7VTRI/OMultiplexed I/O & Peripheral Pin VTR (General)
F9GP10 / RXD3I/OMultiplexed I/O & Peripheral Pin GP10 / RXD3 (UART)
F10GP17 / nRTS3I/OMultiplexed I/O & Peripheral Pin GP17 / nRTS3 (General)
F11GP42 / nIO_PMEI/OMultiplexed I/O & Peripheral Pin GP42 / nIO_PME (General)
G1PCI_CLKI/OMultiplexed I/O & Peripheral Pin PCI_CLK (General)
G2SER_IRQI/OMultiplexed I/O & Peripheral Pin SER_IRQ (General)
G3LDRQ#I/OMultiplexed I/O & Peripheral Pin LDRQ# (General)
G5TEST VSSb =GNDGround Reference Pin (TEST VSSb =)
G6VTRI/OMultiplexed I/O & Peripheral Pin VTR (General)
G7VSSGNDGround Reference Pin (VSS)
G9GP54 / nDSR2I/OMultiplexed I/O & Peripheral Pin GP54 / nDSR2 (General)
G10GP11 / TXD3I/OMultiplexed I/O & Peripheral Pin GP11 / TXD3 (UART)
G11GP16 / nCTS3I/OMultiplexed I/O & Peripheral Pin GP16 / nCTS3 (General)
H1VSSGNDGround Reference Pin (VSS)
H2VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
H3nIDE RSTDRV / GP44_I/OMultiplexed I/O & Peripheral Pin nIDE RSTDRV / GP44_ (UART)
H9GP53 / TXD2(IRTX2)I/OMultiplexed I/O & Peripheral Pin GP53 / TXD2(IRTX2) (UART)
H10PB OUT#_I/OMultiplexed I/O & Peripheral Pin PB OUT#_ (UART)
H11SLP SX#_I/OMultiplexed I/O & Peripheral Pin SLP SX#_ (General)
J1AVSSGNDGround Reference Pin (AVSS)
J2nPCIRST1 / GP45I/OMultiplexed I/O & Peripheral Pin nPCIRST1 / GP45 (UART)
J3nPCIRST3 / GP47I/OMultiplexed I/O & Peripheral Pin nPCIRST3 / GP47 (General)
J4KDAT / GP21I/OMultiplexed I/O & Peripheral Pin KDAT / GP21 (General)
J5GP50 / nRI2I/OMultiplexed I/O & Peripheral Pin GP50 / nRI2 (General)
J6nDTR1 / SYSOPT1I/OMultiplexed I/O & Peripheral Pin nDTR1 / SYSOPT1 (General)
J7nCTS1I/OMultiplexed I/O & Peripheral Pin nCTS1 (General)
J8TXD1 / SIOXNOROUTI/OMultiplexed I/O & Peripheral Pin TXD1 / SIOXNOROUT (UART)
J9GP52 / RXD2(IRRX2)I/OMultiplexed I/O & Peripheral Pin GP52 / RXD2(IRRX2) (UART)
J10GP57 / nDTR2I/OMultiplexed I/O & Peripheral Pin GP57 / nDTR2 (General)
J11PB IN#_I/OMultiplexed I/O & Peripheral Pin PB IN#_ (General)
K1VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
K2nPCIRST2 / GP46I/OMultiplexed I/O & Peripheral Pin nPCIRST2 / GP46 (General)
K3GP27 / nIO SMI / P17_I/OMultiplexed I/O & Peripheral Pin GP27 / nIO SMI / P17_ (General)
K4MCLK / GP33I/OMultiplexed I/O & Peripheral Pin MCLK / GP33 (General)
K5nRTS1 / SYSOPT0I/OMultiplexed I/O & Peripheral Pin nRTS1 / SYSOPT0 (General)
K6nDSR1I/OMultiplexed I/O & Peripheral Pin nDSR1 (General)
K7nRI1I/OMultiplexed I/O & Peripheral Pin nRI1 (General)
K8RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
K9GP51 / nDCD2I/OMultiplexed I/O & Peripheral Pin GP51 / nDCD2 (General)
K10GP56 / nCTS2I/OMultiplexed I/O & Peripheral Pin GP56 / nCTS2 (General)
K11PS ON#_I/OMultiplexed I/O & Peripheral Pin PS ON#_ (UART)
L2KCLK / GP22I/OMultiplexed I/O & Peripheral Pin KCLK / GP22 (General)
L3MDAT / GP32I/OMultiplexed I/O & Peripheral Pin MDAT / GP32 (General)
L4GP36 / nKBDRSTI/OMultiplexed I/O & Peripheral Pin GP36 / nKBDRST (General)
L5GP37 / A20MI/OMultiplexed I/O & Peripheral Pin GP37 / A20M (General)
L6nDCD1I/OMultiplexed I/O & Peripheral Pin nDCD1 (General)
L7VSSGNDGround Reference Pin (VSS)
L8STRAPOPT ( VSSa) =GNDGround Reference Pin (STRAPOPT ( VSSa) =)
L9VTRI/OMultiplexed I/O & Peripheral Pin VTR (General)
L10GP55 / nRTS2 / RESGENI/OMultiplexed I/O & Peripheral Pin GP55 / nRTS2 / RESGEN (General)
PIN A2 REMOTE2 -
I/O
Multiplexed I/O & Peripheral Pin REMOTE2 - (General)
Design note: REMOTE2 -
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: SCH3224-SY (MICROCHIP · WFBGA-100)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
SCH3224-SY (WFBGA-100) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
SCH3224-SY (WFBGA-100) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
SCH3224-SY (WFBGA-100) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SCH3224-SY (WFBGA-100) - 4. Package Dimensions (D×E×A)
WFBGA-100 · 8.00×8.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
SCH3224-SY (WFBGA-100) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
SCH3224-SY (WFBGA-100) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for SCH3224 / SCH3226
P1 · p01_fig01377×200px
SCH3224-SY (WFBGA-100) — LPC IO with 8042 KBC, Reset Generation, HWM and
LPC IO with 8042 KBC, Reset Generation, HWM and
P7 · p07_fig011569×1918px
SCH3224-SY (WFBGA-100) — FIGURE 2-1: SCH3227 PIN DIAGRAM
FIGURE 2-1: SCH3227 PIN DIAGRAM
P7 · p07_fig01P7
SCH3224-SY (WFBGA-100) — Datasheet Page 7 (p07_fig01)
Datasheet Page 7 (p07_fig01)
P54 · p54_fig011782×1504px
SCH3224-SY (WFBGA-100) — FIGURE 6-4: HALF DUPLEX OPERATION WITH DIRECTION CONTROL
FIGURE 6-4: HALF DUPLEX OPERATION WITH DIRECTION CONTROL
P56 · p56_fig011779×1871px
SCH3224-SY (WFBGA-100) — CONTROL PORT BASE ADDRESS + 02H
CONTROL PORT BASE ADDRESS + 02H
P56 · p56_fig01P56
SCH3224-SY (WFBGA-100) — Datasheet Page 56 (p56_fig01)
Datasheet Page 56 (p56_fig01)
P281 · p281_fig011777×2272px
SCH3224-SY (WFBGA-100) — FIGURE 28-1: SCH3227 144-BALL WFBGA PACKAGE OUTLINE; 9 X 9 MM BODY, 0.65MM PITCH
FIGURE 28-1: SCH3227 144-BALL WFBGA PACKAGE OUTLINE; 9 X 9 MM BODY, 0.65MM PITCH
P281 · p281_fig02168×424px
SCH3224-SY (WFBGA-100) — ;
;
P281 · p281_fig01P281
SCH3224-SY (WFBGA-100) — Datasheet Page 281 (p281_fig01)
Datasheet Page 281 (p281_fig01)
P282 · p282_fig011777×2346px
SCH3224-SY (WFBGA-100) — FIGURE 28-2: SCH3226, SCH3224 100-BALL WFBGA PACKAGE OUTLINE; 8 X 8 MM BODY, 0.65MM PITCH
FIGURE 28-2: SCH3226, SCH3224 100-BALL WFBGA PACKAGE OUTLINE; 8 X 8 MM BODY, 0.65MM PITCH
P282 · p282_fig02153×385px
SCH3224-SY (WFBGA-100) — ;
;
P283 · p283_fig011777×2358px
SCH3224-SY (WFBGA-100) — FIGURE 28-3: SCH3222 84-BALL WFBGA PACKAGE OUTLINE; 7 X 7 MM BODY, 0.65MM PITCH
FIGURE 28-3: SCH3222 84-BALL WFBGA PACKAGE OUTLINE; 7 X 7 MM BODY, 0.65MM PITCH
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (SCH3224-SY)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:SCH3224-SY (WFBGA-100) is a 100-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 1.35 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C to +85°C with integrated UART, ADC, IrDA, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
19MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 1.35 mm (A1=0.30 mm)
Package family: BGA (WFBGA-100)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, ADC, IrDA, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — SCH3224 / SCH3226 (4)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (WFBGA-100)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.35mm · e=0.65mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WFBGA-100
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — SCH3224-SY (WFBGA-100)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of SCH3224-SY (WFBGA-100)?

Manufactured by MICROCHIP, the SCH3224-SY is housed in a WFBGA-100 package with 100 pins and a 0.65 mm lead pitch. Key pins include: A2 (REMOTE2 -: Multiplexed I/O & Peripheral Pin REMOTE2 - (General)), A3 (HVSS: Ground Reference Pin (HVSS)), A4 (PWM1: Multiplexed I/O & Peripheral Pin PWM1 (PWM)), A5 (nHWM_INT: Multiplexed I/O & Peripheral Pin nHWM_INT (General)), A6 (PWM3: Multiplexed I/O & Peripheral Pin PWM3 (PWM)), A7 (PWRGD_OUT: Multiplexed I/O & Peripheral Pin PWRGD_OUT (General)).

What are the IPC-7351B PCB Footprint dimensions for SCH3224-SY?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SCH3224-SY (WFBGA-100) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.65 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for SCH3224-SY?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SCH3224-SY (MICROCHIP, WFBGA-100) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & SCH3224 / SCH3226 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A2REMOTE2 -Digital_IOSignal terminal REMOTE2 - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: REMOTE2 -. Supported peripheral buses: General.
A3HVSSGND0V electrical ground return terminal (HVSS) for internal core logic, I/O drivers, and analog sub-blocks.
A4PWM1Digital_IOSignal terminal PWM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM1. Supported peripheral buses: PWM.
A5nHWM_INTDigital_IOSignal terminal nHWM_INT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nHWM_INT. Supported peripheral buses: General.
A6PWM3Digital_IOSignal terminal PWM3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM3. Supported peripheral buses: PWM.
A7PWRGD_OUTDigital_IOSignal terminal PWRGD_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWRGD_OUT. Supported peripheral buses: General.
A8GP62 / nCTS4Digital_IOSignal terminal GP62 / nCTS4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP62 / nCTS4. Supported peripheral buses: General.
A9GP66 / nDSR4Digital_IOSignal terminal GP66 / nDSR4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP66 / nDSR4. Supported peripheral buses: General.
A10VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B1REMOTE1 -Digital_IOSignal terminal REMOTE1 - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: REMOTE1 -. Supported peripheral buses: General.
B2+25V IN ._Power_InPrimary positive power supply input (+25V IN ._) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
B3HVTRDigital_IOSignal terminal HVTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVTR. Supported peripheral buses: General.
B4FANTACH3RF_50OhmSignal terminal FANTACH3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FANTACH3. Supported peripheral buses: General.
B5PWM2Digital_IOSignal terminal PWM2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM2. Supported peripheral buses: PWM.
B6nTHERMTRIPDigital_IOSignal terminal nTHERMTRIP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nTHERMTRIP. Supported peripheral buses: General.
B7PWRGD_PSDigital_IOSignal terminal PWRGD_PS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWRGD_PS. Supported peripheral buses: General.
B8GP67 / nRTS4Digital_IOSignal terminal GP67 / nRTS4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP67 / nRTS4. Supported peripheral buses: General.
B9GP65 / TXD4Digital_IOSignal terminal GP65 / TXD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP65 / TXD4. Supported peripheral buses: UART.
B10nRSMRSTDigital_IOSignal terminal nRSMRST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nRSMRST. Supported peripheral buses: General.
B11CLKI32Digital_IOSignal terminal CLKI32 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLKI32. Supported peripheral buses: General.
C1+5V_INPower_InPrimary positive power supply input (+5V_IN) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
C2+12V_INDigital_IOSignal terminal +12V_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: +12V_IN. Supported peripheral buses: General.
C3GP40 / DRVDEN0(out)Digital_IOSignal terminal GP40 / DRVDEN0(out) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP40 / DRVDEN0(out). Supported peripheral buses: General.
C4FANTACH1RF_50OhmSignal terminal FANTACH1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FANTACH1. Supported peripheral buses: General.
C5FANTACH2RF_50OhmSignal terminal FANTACH2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FANTACH2. Supported peripheral buses: General.
C6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C7GP34 / nDTR4Digital_IOSignal terminal GP34 / nDTR4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP34 / nDTR4. Supported peripheral buses: General.
C8GP64 / RXD4Digital_IOSignal terminal GP64 / RXD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP64 / RXD4. Supported peripheral buses: UART.
C9GP63 / nDCD4Digital_IOSignal terminal GP63 / nDCD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP63 / nDCD4. Supported peripheral buses: General.
C10GP31 / nRI4Digital_IOSignal terminal GP31 / nRI4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP31 / nRI4. Supported peripheral buses: General.
C11GP12 / nDCD3Digital_IOSignal terminal GP12 / nDCD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP12 / nDCD3. Supported peripheral buses: General.
D1LAD2Digital_IOSignal terminal LAD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD2. Supported peripheral buses: General.
D2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D3VTRDigital_IOSignal terminal VTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR. Supported peripheral buses: General.
D9GP61 / nLED2 / CLKODigital_IOSignal terminal GP61 / nLED2 / CLKO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP61 / nLED2 / CLKO. Supported peripheral buses: General.
D10GP60 / nLED1 / WDTDigital_IOSignal terminal GP60 / nLED1 / WDT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP60 / nLED1 / WDT. Supported peripheral buses: General.
D11GP13 / nRI3Digital_IOSignal terminal GP13 / nRI3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP13 / nRI3. Supported peripheral buses: General.
E1LFRAME#Digital_IOSignal terminal LFRAME# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LFRAME#. Supported peripheral buses: General.
E2LAD1Digital_IOSignal terminal LAD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD1. Supported peripheral buses: General.
E3CLOCKIDigital_IOSignal terminal CLOCKI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLOCKI. Supported peripheral buses: General.
E5RESERVED VSSc =GND0V electrical ground return terminal (RESERVED VSSc =) for internal core logic, I/O drivers, and analog sub-blocks.
E6nHWM_INTDigital_IOSignal terminal nHWM_INT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nHWM_INT. Supported peripheral buses: General.
E7nFPRST / GP30Digital_IOSignal terminal nFPRST / GP30 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nFPRST / GP30. Supported peripheral buses: General.
E9GP14 / nDSR3Digital_IOSignal terminal GP14 / nDSR3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP14 / nDSR3. Supported peripheral buses: General.
E10VTRDigital_IOSignal terminal VTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR. Supported peripheral buses: General.
E11GP15 / nDTR3Digital_IOSignal terminal GP15 / nDTR3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP15 / nDTR3. Supported peripheral buses: General.
F1PCI RESET#_Digital_IOActive-low hardware reset terminal (PCI RESET#_): pulling this pin Low resets the processor core and peripherals.
F2LAD3Digital_IOSignal terminal LAD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD3. Supported peripheral buses: General.
F3LAD0Digital_IOSignal terminal LAD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LAD0. Supported peripheral buses: General.
F5RESERVED VSSc =GND0V electrical ground return terminal (RESERVED VSSc =) for internal core logic, I/O drivers, and analog sub-blocks.
F7VTRDigital_IOSignal terminal VTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR. Supported peripheral buses: General.
F9GP10 / RXD3Digital_IOSignal terminal GP10 / RXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP10 / RXD3. Supported peripheral buses: UART.
F10GP17 / nRTS3Digital_IOSignal terminal GP17 / nRTS3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP17 / nRTS3. Supported peripheral buses: General.
F11GP42 / nIO_PMEDigital_IOSignal terminal GP42 / nIO_PME (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP42 / nIO_PME. Supported peripheral buses: General.
G1PCI_CLKDigital_IOSignal terminal PCI_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PCI_CLK. Supported peripheral buses: General.
G2SER_IRQDigital_IOSignal terminal SER_IRQ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SER_IRQ. Supported peripheral buses: General.
G3LDRQ#Digital_IOSignal terminal LDRQ# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LDRQ#. Supported peripheral buses: General.
G5TEST VSSb =GND0V electrical ground return terminal (TEST VSSb =) for internal core logic, I/O drivers, and analog sub-blocks.
G6VTRDigital_IOSignal terminal VTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR. Supported peripheral buses: General.
G7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
G9GP54 / nDSR2Digital_IOSignal terminal GP54 / nDSR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP54 / nDSR2. Supported peripheral buses: General.
G10GP11 / TXD3Digital_IOSignal terminal GP11 / TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP11 / TXD3. Supported peripheral buses: UART.
G11GP16 / nCTS3Digital_IOSignal terminal GP16 / nCTS3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GP16 / nCTS3. Supported peripheral buses: General.
H1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
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