PIC16F648AT-I/ML (QFN-28-EP(6x6)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC16F648AT-I/ML (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC16F648AT-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 4.5V to 5.5V. Key pins include: 1 (RA2: Multiplexed I/O & Peripheral Pin RA2 (General)), 2 (RA3: Multiplexed I/O & Peripheral Pin RA3 (General)), 3 (RA4: Multiplexed I/O & Peripheral Pin RA4 (General)), 4 (RA5: Multiplexed I/O & Peripheral Pin RA5 (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (RA7: Multiplexed I/O & Peripheral Pin RA7 (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC16F648AT-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F648AT-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F648AT-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F648AT-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 6.00mm × 6.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	RA2	I/O	Multiplexed I/O & Peripheral Pin RA2 (General)
2	RA3	I/O	Multiplexed I/O & Peripheral Pin RA3 (General)
3	RA4	I/O	Multiplexed I/O & Peripheral Pin RA4 (General)
4	RA5	I/O	Multiplexed I/O & Peripheral Pin RA5 (General)
5	VSS	GND	Ground Reference Pin (VSS)
6	RA7	I/O	Multiplexed I/O & Peripheral Pin RA7 (General)
7	RA6	I/O	Multiplexed I/O & Peripheral Pin RA6 (General)
8	RC0	I/O	Multiplexed I/O & Peripheral Pin RC0 (General)
9	RC1	I/O	Multiplexed I/O & Peripheral Pin RC1 (General)
10	RC2	I/O	Multiplexed I/O & Peripheral Pin RC2 (General)
11	RC3	I/O	Multiplexed I/O & Peripheral Pin RC3 (General)
12	RC4	I/O	Multiplexed I/O & Peripheral Pin RC4 (General)
13	RC5	I/O	Multiplexed I/O & Peripheral Pin RC5 (General)
14	RC6	I/O	Multiplexed I/O & Peripheral Pin RC6 (General)
15	RC7	I/O	Multiplexed I/O & Peripheral Pin RC7 (General)
16	VSS	GND	Ground Reference Pin (VSS)
17	VDD	Power	Power Supply Input (VDD — 4.5V to 5.5V)
18	RB0	I/O	Multiplexed I/O & Peripheral Pin RB0 (General)
19	RB1	I/O	Multiplexed I/O & Peripheral Pin RB1 (General)
20	RB2	I/O	Multiplexed I/O & Peripheral Pin RB2 (General)
21	RB3	I/O	Multiplexed I/O & Peripheral Pin RB3 (General)
22	RB4	I/O	Multiplexed I/O & Peripheral Pin RB4 (General)
23	RB5	I/O	Multiplexed I/O & Peripheral Pin RB5 (General)
24	STATUS	I/O	Multiplexed I/O & Peripheral Pin STATUS (General)
25	OPTION	I/O	Multiplexed I/O & Peripheral Pin OPTION (General)
26	INTCON	I/O	Multiplexed I/O & Peripheral Pin INTCON (General)
27	PIE1	I/O	Multiplexed I/O & Peripheral Pin PIE1 (General)
28	PIR1	I/O	Multiplexed I/O & Peripheral Pin PIR1 (General)
29	PCON	I/O	Multiplexed I/O & Peripheral Pin PCON (General)

PIN 1 RA2

I/O

Multiplexed I/O & Peripheral Pin RA2 (General)

Design note: Signal terminal RA2 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC16F648AT-I/ML (QFN-28-EP(6x6)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC16F648AT-I/ML (QFN-28-EP(6x6)) - 2. Standard Pinout (Top View)

True package pinout (29 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC16F648AT-I/ML (QFN-28-EP(6x6)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC16F648AT-I/ML (QFN-28-EP(6x6)) - 4. Package Dimensions (D×E×A)

QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC16F648AT-I/ML (QFN-28-EP(6x6)) - 5. Recommended Land Pattern

IPC-7351B Footprint (29 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC16F648AT-I/ML (QFN-28-EP(6x6)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)

Showing 1–9 of 9 uncropped original figures for PIC16F648AT

P2 · p02_fig011777×1640px

PIC16F648AT-I/ML (QFN-28-EP(6x6)) — DS40044G-page 2 © 2009 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Inc

DS40044G-page 2 © 2009 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Inc

P2 · p02_fig02788×285px

PIC16F648AT-I/ML (QFN-28-EP(6x6)) — DS40044G-page 2 © 2009 Microchip Technology Inc.

P58 · p58_fig01867×586px

FIGURE 9-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

P58 · p58_fig02867×558px

FIGURE 9-2: COMPARE MODE OPERATION BLOCK DIAGRAM

P114 · p114_fig01869×373px

PIC16F648AT-I/ML (QFN-28-EP(6x6)) — Note 1: While in this mode, the RB4 pin can no | longer be used as a general purpose I/O pin. | 2: VDD must be 5.0V +10% during erase operations.

Note 1: While in this mode, the RB4 pin can no | longer be used as a general purpose I/O pin. | 2: VDD must be 5.0V +10% during erase operations.

P114 · p114_fig02867×857px

FIGURE 14-18: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION

P114 · p114_fig02P114

Datasheet Page 114 (p114_fig02)

P163 · p163_fig01All Packages in PDF

PIC16F627A/628A/648A

P165 · p165_fig01All Packages in PDF

PIC16F627A/628A/648A - 18-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] - http:/ww.microchip.com/packaging | © 2009 Microchip Technology Inc. DS40044G-page 165 | dêÜè nóÜ§•îé qûÜóó m¶•óîüê qm uîèê$ %&' ûû T†è∞ ÄqmaUÇ |

Technical Specifications & Part Details (PIC16F648AT-I/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC16F648AT-I/ML (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 4.5V to 5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, PWM interfaces.

Operating Supply VoltageV_CC / V_DD

4.5V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

20 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

6.00 × 6.00 × 1.00 mm (A1=0.03 mm)

Package family: QFN (QFN-28-EP(6x6))

Pin Count & Lead PitchN / e

28 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

UART, PWM

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol29 auto-grouped pins

IPC-7351B Land Pattern29 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteEPAD 4.70×4.70mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

6.00 × 6.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.00mm · e=0.65mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-28-EP(6x6)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16F648AT-I/ML (QFN-28-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16F648AT-I/ML (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC16F648AT-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 4.5V to 5.5V. Key pins include: 1 (RA2: Multiplexed I/O & Peripheral Pin RA2 (General)), 2 (RA3: Multiplexed I/O & Peripheral Pin RA3 (General)), 3 (RA4: Multiplexed I/O & Peripheral Pin RA4 (General)), 4 (RA5: Multiplexed I/O & Peripheral Pin RA5 (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (RA7: Multiplexed I/O & Peripheral Pin RA7 (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16F648AT-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F648AT-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F648AT-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F648AT-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & PIC16F648AT Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	RA2	Digital_IO	Signal terminal RA2 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
2	RA3	Digital_IO	Signal terminal RA3 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RA3. Supported peripheral buses: General.
3	RA4	Digital_IO	Signal terminal RA4 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RA4. Supported peripheral buses: General.
4	RA5	Digital_IO	Signal terminal RA5 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RA5. Supported peripheral buses: General.
5	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6	RA7	Digital_IO	Signal terminal RA7 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RA7. Supported peripheral buses: General.
7	RA6	Digital_IO	Signal terminal RA6 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RA6. Supported peripheral buses: General.
8	RC0	Digital_IO	Signal terminal RC0 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RC0. Supported peripheral buses: General.
9	RC1	Digital_IO	Signal terminal RC1 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RC1. Supported peripheral buses: General.
10	RC2	Digital_IO	Signal terminal RC2 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RC2. Supported peripheral buses: General.
11	RC3	Digital_IO	Signal terminal RC3 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RC3. Supported peripheral buses: General.
12	RC4	Digital_IO	Signal terminal RC4 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RC4. Supported peripheral buses: General.
13	RC5	Digital_IO	Signal terminal RC5 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RC5. Supported peripheral buses: General.
14	RC6	Digital_IO	Signal terminal RC6 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RC6. Supported peripheral buses: General.
15	RC7	Digital_IO	Signal terminal RC7 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RC7. Supported peripheral buses: General.
16	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17	VDD	Power_In	Primary positive power supply input (VDD) operating in the 4.5V to 5.5V domain (Max rating: 5.5V).
18	RB0	Digital_IO	Signal terminal RB0 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RB0. Supported peripheral buses: General.
19	RB1	Digital_IO	Signal terminal RB1 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RB1. Supported peripheral buses: General.
20	RB2	Digital_IO	Signal terminal RB2 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RB2. Supported peripheral buses: General.
21	RB3	Digital_IO	Signal terminal RB3 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RB3. Supported peripheral buses: General.
22	RB4	Digital_IO	Signal terminal RB4 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RB4. Supported peripheral buses: General.
23	RB5	Digital_IO	Signal terminal RB5 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RB5. Supported peripheral buses: General.
24	STATUS	Digital_IO	Signal terminal STATUS (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: STATUS. Supported peripheral buses: General.
25	OPTION	Digital_IO	Signal terminal OPTION (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: OPTION. Supported peripheral buses: General.
26	INTCON	Digital_IO	Signal terminal INTCON (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: INTCON. Supported peripheral buses: General.
27	PIE1	Digital_IO	Signal terminal PIE1 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: PIE1. Supported peripheral buses: General.
28	PIR1	Digital_IO	Signal terminal PIR1 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: PIR1. Supported peripheral buses: General.
29	PCON	Digital_IO	Signal terminal PCON (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: PCON. Supported peripheral buses: General.

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