dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8))?

Manufactured by MICROCHIP, the dsPIC33FJ64GP204T-I/ML is housed in a QFN-44-EP(8x8) package with 45 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (RP22(1)/CN18/PMA1/RC6: Multiplexed I/O & Peripheral Pin RP22(1)/CN18/PMA1/RC6 (General)), 3 (RP23(1)/CN17/PMA0/RC7: Multiplexed I/O & Peripheral Pin RP23(1)/CN17/PMA0/RC7 (General)), 4 (RP24(1)/CN20/PMA5/RC8: Multiplexed I/O & Peripheral Pin RP24(1)/CN20/PMA5/RC8 (General)), 5 (RP25(1)/CN19/PMA6/RC9: Multiplexed I/O & Peripheral Pin RP25(1)/CN19/PMA6/RC9 (General)), 6 (VSS: Ground Reference Pin (VSS)).

Q: What are the IPC-7351B PCB Footprint dimensions for dsPIC33FJ64GP204T-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.65 mm, and 45 copper pads plus a central exposed thermal pad (EPAD) of 6.45 × 6.45 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for dsPIC33FJ64GP204T-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for dsPIC33FJ64GP204T-I/ML (MICROCHIP, QFN-44-EP(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 8.00mm × 8.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (45/45)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	IO1	I/O	General Purpose Digital I/O Pin IO1
2	RP22(1)/CN18/PMA1/RC6	I/O	Multiplexed I/O & Peripheral Pin RP22(1)/CN18/PMA1/RC6 (General)
3	RP23(1)/CN17/PMA0/RC7	I/O	Multiplexed I/O & Peripheral Pin RP23(1)/CN17/PMA0/RC7 (General)
4	RP24(1)/CN20/PMA5/RC8	I/O	Multiplexed I/O & Peripheral Pin RP24(1)/CN20/PMA5/RC8 (General)
5	RP25(1)/CN19/PMA6/RC9	I/O	Multiplexed I/O & Peripheral Pin RP25(1)/CN19/PMA6/RC9 (General)
6	VSS	GND	Ground Reference Pin (VSS)
7	VCAP	I/O	Multiplexed I/O & Peripheral Pin VCAP (General)
8	IO0	I/O	GPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9	IO4	I/O	GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10	IO5	I/O	GPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4
11	IO6	I/O	GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12	TMS/PMA10/RA10	I/O	Multiplexed I/O & Peripheral Pin TMS/PMA10/RA10 (General)
13	TCK/PMA7/RA7	I/O	Multiplexed I/O & Peripheral Pin TCK/PMA7/RA7 (General)
14	IO16	I/O	GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15	IO17	I/O	GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16	AVSS	GND	Ground Reference Pin (AVSS)
17	AVDD	Power	Power Supply Input (AVDD — 3.0V to 3.6V)
18	/MCLR	I/O	Multiplexed I/O & Peripheral Pin /MCLR (General)
19	AN0/VREF+/CN2/RA0	Analog	Multiplexed I/O & Peripheral Pin AN0/VREF+/CN2/RA0 (General)
20	AN1/VREF-/CN3/RA1	Analog	Multiplexed I/O & Peripheral Pin AN1/VREF-/CN3/RA1 (General)
21	IO10	I/O	GPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22	IO11	I/O	GPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23	IO12	I/O	GPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24	IO13	I/O	GPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ
25	IO14	I/O	GPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP
26	IO21	I/O	GPIO21 / RTC_GPIO21
27	IO47	I/O	GPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28	VDD	Power	Power Supply Input (VDD — 3.0V to 3.6V)
29	VSS	GND	Ground Reference Pin (VSS)
30	OSC1/CLKI/CN30/RA2	I/O	Multiplexed I/O & Peripheral Pin OSC1/CLKI/CN30/RA2 (RTC/CLK)
31	OSC2/CLKO/CN29/RA3	I/O	Multiplexed I/O & Peripheral Pin OSC2/CLKO/CN29/RA3 (RTC/CLK)
32	TDO/PMA8/RA8	I/O	Multiplexed I/O & Peripheral Pin TDO/PMA8/RA8 (General)
33	SOSCI/RP4(1)/CN1/RB4	I/O	Multiplexed I/O & Peripheral Pin SOSCI/RP4(1)/CN1/RB4 (General)
34	SOSCO/T1CK/CN0/RA4	I/O	Multiplexed I/O & Peripheral Pin SOSCO/T1CK/CN0/RA4 (General)
35	TDI/PMA9/RA9	I/O	Multiplexed I/O & Peripheral Pin TDI/PMA9/RA9 (General)
36	RP19(1)/CN28/PMBE/RC3	I/O	Multiplexed I/O & Peripheral Pin RP19(1)/CN28/PMBE/RC3 (General)
37	RP20(1)/CN25/PMA4/RC4	I/O	Multiplexed I/O & Peripheral Pin RP20(1)/CN25/PMA4/RC4 (General)
38	RP21(1)/CN26/PMA3/RC5	I/O	Multiplexed I/O & Peripheral Pin RP21(1)/CN26/PMA3/RC5 (General)
39	VSS	GND	Exposed Thermal & Ground Pad (VSS)
40	VDD	Power	Power Supply Input (VDD — 3.0V to 3.6V)
41	IO41	I/O	General Purpose Digital I/O Pin IO41
42	IO42	I/O	General Purpose Digital I/O Pin IO42
43	IO43	I/O	General Purpose Digital I/O Pin IO43
44	IO44	I/O	General Purpose Digital I/O Pin IO44
45	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 IO1

I/O

General Purpose Digital I/O Pin IO1

Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) - 2. Standard Pinout (Top View)

True package pinout (45 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) - 4. Package Dimensions (D×E×A)

QFN-44-EP(8x8) · 8.00×8.00mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) - 5. Recommended Land Pattern

IPC-7351B Footprint (45 Pads)Expand ›

6. Application SchematicSCHEMATIC

dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)

Showing 1–12 of 12 uncropped original figures for DSPIC33FJ128 / DSPIC33FJ64G

P1 · p01_fig01376×200px

16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Advanced Analog

P14 · p14_fig011777×2492px

dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) — FIGURE 1-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 BLOCK DIAGRAM PSV and Table Data Access Control Block

FIGURE 1-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 BLOCK DIAGRAM PSV and Table Data Access Control Block

P71 · p71_fig011625×913px

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

P71 · p71_fig021777×1030px

FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS

P72 · p72_fig01867×655px

dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) — Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished.

Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished.

P72 · p72_fig021783×380px

dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) — EQUATION 5-1: PROGRAMMING TIME | For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN<5:0> bits (see Register 9-4) are set to ‘b111111, the minimum row write time is equal to Equation 5-2. | 5.5.1 KEY

EQUATION 5-1: PROGRAMMING TIME | For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN<5:0> bits (see Register 9-4) are set to ‘b111111, the minimum row write time is equal to Equation 5-2. | 5.5.1 KEY

P165 · p165_fig011478×506px

dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) — 11.8.1 KEY RESOURCES | • Section 10. “I/O Ports” (DS70193) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools | Note: In the event you are n

11.8.1 KEY RESOURCES | • Section 10. “I/O Ports” (DS70193) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools | Note: In the event you are n

P319 · p319_fig01867×890px

FIGURE 27-1: CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1,2,3)

P319 · p319_fig01P319

Datasheet Page 319 (p319_fig01)

P407 · p407_fig011777×2604px

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

P414 · p414_fig011777×2341px

dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) — DS70292G-page 414 © 2007-2012 Microchip Technology Inc.

P414 · p414_fig01P414

Datasheet Page 414 (p414_fig01)

Technical Specifications & Part Details (dsPIC33FJ64GP204T-I/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) is a 44-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 3.0V to 3.6V supply operation across -40°C to +125°C with integrated UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

3.0V to 3.6V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +125°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

7.37 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

8.00 × 8.00 × 0.90 mm (A1=0.03 mm)

Package family: QFN (QFN-44-EP(8x8))

Pin Count & Lead PitchN / e

44 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol45 auto-grouped pins

IPC-7351B Land Pattern45 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteEPAD 6.45×6.45mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-44-EP(8x8))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

8.00 × 8.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.90mm · e=0.65mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

45P / 45Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-44-EP(8x8)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8))?

Manufactured by MICROCHIP, the dsPIC33FJ64GP204T-I/ML is housed in a QFN-44-EP(8x8) package with 45 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (RP22(1)/CN18/PMA1/RC6: Multiplexed I/O & Peripheral Pin RP22(1)/CN18/PMA1/RC6 (General)), 3 (RP23(1)/CN17/PMA0/RC7: Multiplexed I/O & Peripheral Pin RP23(1)/CN17/PMA0/RC7 (General)), 4 (RP24(1)/CN20/PMA5/RC8: Multiplexed I/O & Peripheral Pin RP24(1)/CN20/PMA5/RC8 (General)), 5 (RP25(1)/CN19/PMA6/RC9: Multiplexed I/O & Peripheral Pin RP25(1)/CN19/PMA6/RC9 (General)), 6 (VSS: Ground Reference Pin (VSS)).

What are the IPC-7351B PCB Footprint dimensions for dsPIC33FJ64GP204T-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), dsPIC33FJ64GP204T-I/ML (QFN-44-EP(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.65 mm, and 45 copper pads plus a central exposed thermal pad (EPAD) of 6.45 × 6.45 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for dsPIC33FJ64GP204T-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for dsPIC33FJ64GP204T-I/ML (MICROCHIP, QFN-44-EP(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (45 pins) & DSPIC33FJ128 / DSPIC33FJ64G Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	IO1	Digital_IO	General Purpose Digital I/O Pin IO1
2	RP22(1)/CN18/PMA1/RC6	Digital_IO	Signal terminal RP22(1)/CN18/PMA1/RC6 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP22(1)/CN18/PMA1/RC6. Supported peripheral buses: General.
3	RP23(1)/CN17/PMA0/RC7	Digital_IO	Signal terminal RP23(1)/CN17/PMA0/RC7 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP23(1)/CN17/PMA0/RC7. Supported peripheral buses: General.
4	RP24(1)/CN20/PMA5/RC8	Digital_IO	Signal terminal RP24(1)/CN20/PMA5/RC8 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP24(1)/CN20/PMA5/RC8. Supported peripheral buses: General.
5	RP25(1)/CN19/PMA6/RC9	Digital_IO	Signal terminal RP25(1)/CN19/PMA6/RC9 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP25(1)/CN19/PMA6/RC9. Supported peripheral buses: General.
6	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
7	VCAP	Digital_IO	Signal terminal VCAP (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
8	IO0	Digital_IO	GPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9	IO4	Digital_IO	GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10	IO5	Digital_IO	GPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4
11	IO6	Digital_IO	GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12	TMS/PMA10/RA10	Digital_IO	Signal terminal TMS/PMA10/RA10 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TMS/PMA10/RA10. Supported peripheral buses: General.
13	TCK/PMA7/RA7	Digital_IO	Signal terminal TCK/PMA7/RA7 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TCK/PMA7/RA7. Supported peripheral buses: General.
14	IO16	Digital_IO	GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15	IO17	Digital_IO	GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16	AVSS	GND	0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
17	AVDD	Power_In	Primary positive power supply input (AVDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
18	/MCLR	Digital_IO	Signal terminal /MCLR (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: /MCLR. Supported peripheral buses: General.
19	AN0/VREF+/CN2/RA0	Analog	Signal terminal AN0/VREF+/CN2/RA0 (Analog, 3.0V to 3.6V domain). Multiplexed alternate functions: AN0/VREF+/CN2/RA0. Supported peripheral buses: General.
20	AN1/VREF-/CN3/RA1	Analog	Signal terminal AN1/VREF-/CN3/RA1 (Analog, 3.0V to 3.6V domain). Multiplexed alternate functions: AN1/VREF-/CN3/RA1. Supported peripheral buses: General.
21	IO10	Digital_IO	GPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22	IO11	Digital_IO	GPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23	IO12	Digital_IO	GPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24	IO13	Digital_IO	GPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ
25	IO14	Digital_IO	GPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP
26	IO21	Digital_IO	GPIO21 / RTC_GPIO21
27	IO47	Digital_IO	GPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
29	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
30	OSC1/CLKI/CN30/RA2	Digital_IO	Signal terminal OSC1/CLKI/CN30/RA2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC1/CLKI/CN30/RA2. Supported peripheral buses: RTC/CLK.
31	OSC2/CLKO/CN29/RA3	Digital_IO	Signal terminal OSC2/CLKO/CN29/RA3 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC2/CLKO/CN29/RA3. Supported peripheral buses: RTC/CLK.
32	TDO/PMA8/RA8	Digital_IO	Signal terminal TDO/PMA8/RA8 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TDO/PMA8/RA8. Supported peripheral buses: General.
33	SOSCI/RP4(1)/CN1/RB4	Digital_IO	Signal terminal SOSCI/RP4(1)/CN1/RB4 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SOSCI/RP4(1)/CN1/RB4. Supported peripheral buses: General.
34	SOSCO/T1CK/CN0/RA4	Digital_IO	Signal terminal SOSCO/T1CK/CN0/RA4 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SOSCO/T1CK/CN0/RA4. Supported peripheral buses: General.
35	TDI/PMA9/RA9	Digital_IO	Signal terminal TDI/PMA9/RA9 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TDI/PMA9/RA9. Supported peripheral buses: General.
36	RP19(1)/CN28/PMBE/RC3	Digital_IO	Signal terminal RP19(1)/CN28/PMBE/RC3 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP19(1)/CN28/PMBE/RC3. Supported peripheral buses: General.
37	RP20(1)/CN25/PMA4/RC4	Digital_IO	Signal terminal RP20(1)/CN25/PMA4/RC4 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP20(1)/CN25/PMA4/RC4. Supported peripheral buses: General.
38	RP21(1)/CN26/PMA3/RC5	Digital_IO	Signal terminal RP21(1)/CN26/PMA3/RC5 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP21(1)/CN26/PMA3/RC5. Supported peripheral buses: General.
39	VSS	GND	Bottom exposed die attach pad (VSS) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
40	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
41	IO41	Digital_IO	General Purpose Digital I/O Pin IO41
42	IO42	Digital_IO	General Purpose Digital I/O Pin IO42
43	IO43	Digital_IO	General Purpose Digital I/O Pin IO43
44	IO44	Digital_IO	General Purpose Digital I/O Pin IO44
45	EP	GND	Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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