QFN-28-EP(6x6) · 29P
29P6.0×6.0×1.00mmP=0.5mm
DSPIC33EV32G / DSPIC33EV128 (QFN-28-EP(6x6))
Synchronized Pinout (Symbol / 2D / 3D) (29/29)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | IO1 | I/O | General Purpose Digital I/O Pin IO1 |
| 2 | IO2 | I/O | General Purpose Digital I/O Pin IO2 |
| 3 | 3V3 | Power | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | NC | NC | No Connect (Leave Floating) |
| 5 | VSS | GND | Ground Reference Pin (VSS) |
| 6 | IO3 | I/O | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | OSC2/CLKO/RPI19/RA3 | I/O | Multiplexed I/O & Peripheral Pin OSC2/CLKO/RPI19/RA3 (RTC/CLK) |
| 8 | FLT32/RP36/RB4 | I/O | Multiplexed I/O & Peripheral Pin FLT32/RP36/RB4 (General) |
| 9 | IO4 | I/O | GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3 |
| 10 | VDD | Power | Power Supply Input (VDD — 4.5V to 5.5V) |
| 11 | PGED2/SDA1/RP37/RB5 | I/O | Multiplexed I/O & Peripheral Pin PGED2/SDA1/RP37/RB5 (I2C) |
| 12 | PGEC2/SCL1/RP38/RB6 | I/O | Multiplexed I/O & Peripheral Pin PGEC2/SCL1/RP38/RB6 (I2C) |
| 13 | IO15 | I/O | GPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P |
| 14 | IO16 | I/O | GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N |
| 15 | IO17 | I/O | GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6 |
| 16 | VSS | GND | Ground Reference Pin (VSS) |
| 17 | VCAP | I/O | Multiplexed I/O & Peripheral Pin VCAP (General) |
| 18 | RP42/PWM3H/RB10 | I/O | Multiplexed I/O & Peripheral Pin RP42/PWM3H/RB10 (PWM) |
| 19 | RP43/PWM3L/RB11 | I/O | Multiplexed I/O & Peripheral Pin RP43/PWM3L/RB11 (PWM) |
| 20 | RPI44/PWM2H/RB12 | I/O | Multiplexed I/O & Peripheral Pin RPI44/PWM2H/RB12 (PWM) |
| 21 | RPI45/PWM2L/CTPLS/RB13 | I/O | Multiplexed I/O & Peripheral Pin RPI45/PWM2L/CTPLS/RB13 (PWM) |
| 22 | RPI46/PWM1H/T3CK/RB14 | I/O | Multiplexed I/O & Peripheral Pin RPI46/PWM1H/T3CK/RB14 (PWM) |
| 23 | RPI47/PWM1L/T5CK/RB15 | I/O | Multiplexed I/O & Peripheral Pin RPI47/PWM1L/T5CK/RB15 (PWM) |
| 24 | AVSS | GND | Ground Reference Pin (AVSS) |
| 25 | AVDD | Power | Power Supply Input (AVDD — 4.5V to 5.5V) |
| 26 | MCLR# | I/O | Multiplexed I/O & Peripheral Pin MCLR# (General) |
| 27 | IO47 | I/O | GPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF |
| 28 | IO33 | I/O | GPIO33 / FSPIHD / SUBSPIHD / SPIIO4 |
| 29 | EP | GND | Exposed Thermal & Ground Pad (EP) |
PIN 1 IO1
I/OGeneral Purpose Digital I/O Pin IO1
Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.
IPC-7351B Solder Density & Span C/G/Z Tuner
Extracted Drawings Gallery (6 Standard Drawings + 10 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for DSPIC33EV32G / DSPIC33EV128
P1 · p01_fig01376×200px
P17 · p17_fig011777×1763px
P87 · p87_fig011777×949px
P328 · p328_fig01867×886px
P477 · p477_fig011779×2732px
P482 · p482_fig011778×2432px
P482 · p482_fig01P482
P483 · p483_fig011779×2732px
P483 · p483_fig01P483
P489 · p489_fig011779×2732px
Technical Specifications & Part Details (dsPIC33EV32GM002T-I/MM)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:dsPIC33EV32GM002T-I/MM (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.00 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 4.5V to 5.5V supply operation across 0°C to +85°C with integrated UART, SPI, I2C, ADC, DAC, PWM, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
4.5V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
0°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(6x6))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, DAC, PWM, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol29 auto-grouped pins
IPC-7351B Land Pattern29 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteEPAD 6.60×6.60mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — DSPIC33EV32G / DSPIC33EV128 (2)
TQFP-48(7x7) · 48P
48P7.0×7.0×1.20mmP=0.5mm
DSPIC33EV32G / DSPIC33EV128 (TQFP-48(7x7))
Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.50mm
Pad Size (W × L)Level B
0.35 × 0.85 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-28-EP(6x6) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — dsPIC33EV32GM002T-I/MM (QFN-28-EP(6x6))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of dsPIC33EV32GM002T-I/MM (QFN-28-EP(6x6))?
Manufactured by MICROCHIP, the dsPIC33EV32GM002T-I/MM is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 4.5V to 5.5V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (VSS: Ground Reference Pin (VSS)), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).
What are the IPC-7351B PCB Footprint dimensions for dsPIC33EV32GM002T-I/MM?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), dsPIC33EV32GM002T-I/MM (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.50 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 6.60 × 6.60 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for dsPIC33EV32GM002T-I/MM?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for dsPIC33EV32GM002T-I/MM (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (29 pins) & DSPIC33EV32G / DSPIC33EV128 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | IO1 | Digital_IO | General Purpose Digital I/O Pin IO1 |
| 2 | IO2 | Digital_IO | General Purpose Digital I/O Pin IO2 |
| 3 | 3V3 | Power_In | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | NC | No_Connect | No Connect (Leave Floating) |
| 5 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 6 | IO3 | Digital_IO | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | OSC2/CLKO/RPI19/RA3 | Digital_IO | Signal terminal OSC2/CLKO/RPI19/RA3 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: OSC2/CLKO/RPI19/RA3. Supported peripheral buses: RTC/CLK. |
| 8 | FLT32/RP36/RB4 | Digital_IO | Signal terminal FLT32/RP36/RB4 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: FLT32/RP36/RB4. Supported peripheral buses: General. |
| 9 | IO4 | Digital_IO | GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3 |
| 10 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 4.5V to 5.5V domain (Max rating: 5.5V). |
| 11 | PGED2/SDA1/RP37/RB5 | Digital_IO | Signal terminal PGED2/SDA1/RP37/RB5 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: PGED2/SDA1/RP37/RB5. Supported peripheral buses: I2C. |
| 12 | PGEC2/SCL1/RP38/RB6 | Digital_IO | Signal terminal PGEC2/SCL1/RP38/RB6 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: PGEC2/SCL1/RP38/RB6. Supported peripheral buses: I2C. |
| 13 | IO15 | Digital_IO | GPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P |
| 14 | IO16 | Digital_IO | GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N |
| 15 | IO17 | Digital_IO | GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6 |
| 16 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 17 | VCAP | Digital_IO | Signal terminal VCAP (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General. |
| 18 | RP42/PWM3H/RB10 | Digital_IO | Signal terminal RP42/PWM3H/RB10 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RP42/PWM3H/RB10. Supported peripheral buses: PWM. |
| 19 | RP43/PWM3L/RB11 | Digital_IO | Signal terminal RP43/PWM3L/RB11 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RP43/PWM3L/RB11. Supported peripheral buses: PWM. |
| 20 | RPI44/PWM2H/RB12 | Digital_IO | Signal terminal RPI44/PWM2H/RB12 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RPI44/PWM2H/RB12. Supported peripheral buses: PWM. |
| 21 | RPI45/PWM2L/CTPLS/RB13 | Digital_IO | Signal terminal RPI45/PWM2L/CTPLS/RB13 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RPI45/PWM2L/CTPLS/RB13. Supported peripheral buses: PWM. |
| 22 | RPI46/PWM1H/T3CK/RB14 | Digital_IO | Signal terminal RPI46/PWM1H/T3CK/RB14 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RPI46/PWM1H/T3CK/RB14. Supported peripheral buses: PWM. |
| 23 | RPI47/PWM1L/T5CK/RB15 | Digital_IO | Signal terminal RPI47/PWM1L/T5CK/RB15 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: RPI47/PWM1L/T5CK/RB15. Supported peripheral buses: PWM. |
| 24 | AVSS | GND | 0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 25 | AVDD | Power_In | Primary positive power supply input (AVDD) operating in the 4.5V to 5.5V domain (Max rating: 5.5V). |
| 26 | MCLR# | Digital_IO | Signal terminal MCLR# (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General. |
| 27 | IO47 | Digital_IO | GPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF |
| 28 | IO33 | Digital_IO | GPIO33 / FSPIHD / SUBSPIHD / SPIIO4 |
| 29 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |