TC1174VUATR (MSOP-8) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of TC1174VUATR (MSOP-8)?

Manufactured by MICROCHIP, the TC1174VUATR is housed in a MSOP-8 package with 8 pins and a 0.65 mm lead pitch. Key pins include: 1 (V OUT: Multiplexed I/O & Peripheral Pin V OUT (General)), 2 (GND: Ground Reference Pin (GND)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (ADJ: Multiplexed I/O & Peripheral Pin ADJ (General)), 5 (Bypass: Multiplexed I/O & Peripheral Pin Bypass (General)), 6 (SHDN: Multiplexed I/O & Peripheral Pin SHDN (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for TC1174VUATR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), TC1174VUATR (MSOP-8) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.65 mm, and 8 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for TC1174VUATR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for TC1174VUATR (MICROCHIP, MSOP-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 3.00mm × 3.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (8/8)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	V OUT	I/O	Multiplexed I/O & Peripheral Pin V OUT (General)
2	GND	GND	Ground Reference Pin (GND)
3	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
4	ADJ	I/O	Multiplexed I/O & Peripheral Pin ADJ (General)
5	Bypass	I/O	Multiplexed I/O & Peripheral Pin Bypass (General)
6	SHDN	I/O	Multiplexed I/O & Peripheral Pin SHDN (General)
7	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
8	V IN	I/O	Multiplexed I/O & Peripheral Pin V IN (General)

PIN 1 V OUT

I/O

Multiplexed I/O & Peripheral Pin V OUT (General)

Design note: Regulatedvoltageoutput .

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

TC1174VUATR (MSOP-8) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

TC1174VUATR (MSOP-8) - 2. Standard Pinout (Top View)

True package pinout (8 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

TC1174VUATR (MSOP-8) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

TC1174VUATR (MSOP-8) - 4. Package Dimensions (D×E×A)

MSOP-8 · 3.00×3.00mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

TC1174VUATR (MSOP-8) - 5. Recommended Land Pattern

IPC-7351B Footprint (8 Pads)Expand ›

6. Application SchematicSCHEMATIC

TC1174VUATR (MSOP-8) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)

Showing 1–7 of 7 uncropped original figures for TC1174

P7 · p07_fig01EXACT PACKAGE

6.0 PACKAGING INFORMATION

P8 · p08_fig01EXACT PACKAGE

6.3 Package Dimensions

P1 · p01_fig011778×1280px

 2002-2012 Microchip Technology Inc. DS21363C-page 1

P1 · p01_fig01P1

Datasheet Page 1 (p01_fig01)

P4 · p04_fig011358×550px

FIGURE 3-1: TYPICAL APPLICATION CIRCUIT 8 VOUT VOUT

P8 · p08_fig01P8

Datasheet Page 8 (p08_fig01)

P9 · p09_fig011394×1105px

TC1174VUATR (MSOP-8) — .050 (1.27) TYP. | 8° MAX. | PIN 1 | .244 (6.20) .228 (5.79) .157 (3.99) .150 (3.81) | .197 (5.00) .189 (4.80) | .020 (0.51) .013 (0.33) | .010 (0.25) .004 (0.10) | .069 (1.75) .053 (1.35) .010 (0.25) .007 (0.18) | .050 (1.27) .016 (0.40) |

.050 (1.27) TYP. | 8° MAX. | PIN 1 | .244 (6.20) .228 (5.79) .157 (3.99) .150 (3.81) | .197 (5.00) .189 (4.80) | .020 (0.51) .013 (0.33) | .010 (0.25) .004 (0.10) | .069 (1.75) .053 (1.35) .010 (0.25) .007 (0.18) | .050 (1.27) .016 (0.40) |

Technical Specifications & Part Details (TC1174VUATR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:TC1174VUATR (MSOP-8) is a 8-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 1.10 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C to +125°C with integrated Standard I/O / Passive interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +125°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

1kHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

300mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

3.00 × 3.00 × 1.10 mm (A1=0.08 mm)

Package family: TSSOP (MSOP-8)

Pin Count & Lead PitchN / e

8 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Standard I/O / Passive

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol8 auto-grouped pins

IPC-7351B Land Pattern8 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (MSOP-8)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

3.00 × 3.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.10mm · e=0.65mm

Pad Size (W × L)Level B

0.40 × 1.25 mm

Pins / Total PadsTopology

8P / 8Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit MSOP-8	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — TC1174VUATR (MSOP-8)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of TC1174VUATR (MSOP-8)?

Manufactured by MICROCHIP, the TC1174VUATR is housed in a MSOP-8 package with 8 pins and a 0.65 mm lead pitch. Key pins include: 1 (V OUT: Multiplexed I/O & Peripheral Pin V OUT (General)), 2 (GND: Ground Reference Pin (GND)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (ADJ: Multiplexed I/O & Peripheral Pin ADJ (General)), 5 (Bypass: Multiplexed I/O & Peripheral Pin Bypass (General)), 6 (SHDN: Multiplexed I/O & Peripheral Pin SHDN (General)).

What are the IPC-7351B PCB Footprint dimensions for TC1174VUATR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), TC1174VUATR (MSOP-8) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.65 mm, and 8 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for TC1174VUATR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for TC1174VUATR (MICROCHIP, MSOP-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (8 pins) & TC1174 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	V OUT	Digital_IO	Signal terminal V OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V OUT. Supported peripheral buses: General.
2	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
4	ADJ	Digital_IO	Signal terminal ADJ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ADJ. Supported peripheral buses: General.
5	Bypass	Digital_IO	Signal terminal Bypass (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Bypass. Supported peripheral buses: General.
6	SHDN	Digital_IO	Signal terminal SHDN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SHDN. Supported peripheral buses: General.
7	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
8	V IN	Digital_IO	Signal terminal V IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V IN. Supported peripheral buses: General.

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