ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) — Symbol, Footprint IPC-7351B & 3D STEP Model

ESP32-PICO-V3-ZERO

ESPRESSIFID: C6244699WIRELM-SMD_ESP32-PICO-V3-ZERO · 77 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO)1NC2NC3DBG RXD/IO3_4DBG TXD/IO1_5NC6NC7NC8NC9NC10NC11NC12NC13NC14NC15NC16NC17NC18NC19EN20GND21GND22VDD3323GND24GND25GND26GND27GND28GND29GND30GND31GND32GND33NC34NC35NC36NC37GND38NC39NC77GND76GND75GND74GND73GND72GND71GND70GND69GND68GND67GND66GND65GND64GND63GND62GND61GND60GND59GND58GND57GND56GND55GND54GND53GND52GND51GND50GND49GND48NC47INT B/IO27_46NC45U1RXD/IO2244GND43VDD3342GND41U1TXD/IO1940NCGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.855.950.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8-55.9mm
2. 2D FOOTPRINT
ANTENNA KEEPOUT (7.0mm)1234567891011121314151665686766171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364707172737475767769E=16.00mm · Pitch e=0.80mmD=23.00mm-14-12-10-8-6-4-2024681012141715131197531-1-3-5-7-9-11-13-15-17mm
3. 3D CAD MODEL
Package Body: 16.00mm × 23.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (77/77)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1NCI/OMultiplexed I/O & Peripheral Pin NC (General)
2NCI/OMultiplexed I/O & Peripheral Pin NC (General)
3DBG RXD/IO3_I/OMultiplexed I/O & Peripheral Pin DBG RXD/IO3_ (UART)
4DBG TXD/IO1_I/OMultiplexed I/O & Peripheral Pin DBG TXD/IO1_ (UART)
5NCI/OMultiplexed I/O & Peripheral Pin NC (General)
6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
7NCI/OMultiplexed I/O & Peripheral Pin NC (General)
8NCI/OMultiplexed I/O & Peripheral Pin NC (General)
9NCI/OMultiplexed I/O & Peripheral Pin NC (General)
10NCI/OMultiplexed I/O & Peripheral Pin NC (General)
11NCI/OMultiplexed I/O & Peripheral Pin NC (General)
12NCI/OMultiplexed I/O & Peripheral Pin NC (General)
13NCI/OMultiplexed I/O & Peripheral Pin NC (General)
14NCI/OMultiplexed I/O & Peripheral Pin NC (General)
15NCI/OMultiplexed I/O & Peripheral Pin NC (General)
16NCI/OMultiplexed I/O & Peripheral Pin NC (General)
17NCI/OMultiplexed I/O & Peripheral Pin NC (General)
18NCI/OMultiplexed I/O & Peripheral Pin NC (General)
19ENISystem Enable & Hardware Reset (EN)
20GNDGNDGround Reference Pin (GND)
21GNDGNDGround Reference Pin (GND)
22VDD33PowerPower Supply Input (VDD33 — 3.3V VDD3P3 (3.0V ~ 3.6V))
23GNDGNDGround Reference Pin (GND)
24GNDGNDGround Reference Pin (GND)
25GNDGNDGround Reference Pin (GND)
26GNDGNDGround Reference Pin (GND)
27GNDGNDGround Reference Pin (GND)
28GNDGNDGround Reference Pin (GND)
29GNDGNDGround Reference Pin (GND)
30GNDGNDGround Reference Pin (GND)
31GNDGNDGround Reference Pin (GND)
32GNDGNDGround Reference Pin (GND)
33NCI/OMultiplexed I/O & Peripheral Pin NC (General)
34NCI/OMultiplexed I/O & Peripheral Pin NC (General)
35NCI/OMultiplexed I/O & Peripheral Pin NC (General)
36NCI/OMultiplexed I/O & Peripheral Pin NC (General)
37GNDGNDGround Reference Pin (GND)
38NCI/OMultiplexed I/O & Peripheral Pin NC (General)
39NCI/OMultiplexed I/O & Peripheral Pin NC (General)
40NCI/OMultiplexed I/O & Peripheral Pin NC (General)
41U1TXD/IO19I/OMultiplexed I/O & Peripheral Pin U1TXD/IO19 (UART)
42GNDGNDGround Reference Pin (GND)
43VDD33PowerPower Supply Input (VDD33 — 3.3V VDD3P3 (3.0V ~ 3.6V))
44GNDGNDGround Reference Pin (GND)
45U1RXD/IO22I/OMultiplexed I/O & Peripheral Pin U1RXD/IO22 (UART)
46NCI/OMultiplexed I/O & Peripheral Pin NC (General)
47INT B/IO27_I/OMultiplexed I/O & Peripheral Pin INT B/IO27_ (General)
48NCI/OMultiplexed I/O & Peripheral Pin NC (General)
49GNDGNDExposed Thermal & Ground Pad (GND)
50GNDGNDGround Reference Pin (GND)
51GNDGNDGround Reference Pin (GND)
52GNDGNDGround Reference Pin (GND)
53GNDGNDGround Reference Pin (GND)
54GNDGNDGround Reference Pin (GND)
55GNDGNDGround Reference Pin (GND)
56GNDGNDGround Reference Pin (GND)
57GNDGNDExposed Thermal & Ground Pad (GND)
58GNDGNDGround Reference Pin (GND)
59GNDGNDGround Reference Pin (GND)
60GNDGNDGround Reference Pin (GND)
61GNDGNDGround Reference Pin (GND)
62GNDGNDGround Reference Pin (GND)
63GNDGNDGround Reference Pin (GND)
64GNDGNDGround Reference Pin (GND)
65GNDGNDExposed Thermal & Ground Pad (GND)
66GNDGNDGround Reference Pin (GND)
67GNDGNDGround Reference Pin (GND)
68GNDGNDGround Reference Pin (GND)
69GNDGNDGround Reference Pin (GND)
70GNDGNDGround Reference Pin (GND)
71GNDGNDGround Reference Pin (GND)
72GNDGNDGround Reference Pin (GND)
73GNDGNDGround Reference Pin (GND)
74GNDGNDGround Reference Pin (GND)
75GNDGNDGround Reference Pin (GND)
76GNDGNDGround Reference Pin (GND)
77GNDGNDGround Reference Pin (GND)
PIN 1 NC
I/O
Multiplexed I/O & Peripheral Pin NC (General)
Design note: Donotconnect Thesepinsmustbeleftfloating . .
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ESP32-PICO-V3-ZERO (ESPRESSIF · WIRELM-SMD_ESP32-PICO-V3-ZERO)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) - 2. Standard Pinout (Top View)
True package pinout (77 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) - 4. Package Dimensions (D×E×A)
WIRELM-SMD_ESP32-PICO-V3-ZERO · 16.00×23.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) - 5. Recommended Land Pattern
IPC-7351B Footprint (77 Pads)Expand ›
6. Application SchematicSCHEMATIC
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for ESP32-PICO
P1 · p01_fig01EXACT PACKAGE
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) — ESP32-PICO-V3-ZERO
ESP32-PICO-V3-ZERO
P20 · p20_fig01EXACT PACKAGE
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) — Figure 4: Physical Dimensions
Figure 4: Physical Dimensions
P1 · p01_fig02722×315px
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) — www.espressif.com
www.espressif.com
P9 · p09_fig011281×1425px
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) — Figure 2: Pin Layout (Top View)
Figure 2: Pin Layout (Top View)
P19 · p19_fig011488×1126px
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) — PWR_EN INT_B/IO27 U1TXD/IO19 U1RXD/IO22
PWR_EN INT_B/IO27 U1TXD/IO19 U1RXD/IO22
P19 · p19_fig02996×452px
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) — GND GND
GND GND
P19 · p19_fig01P19
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) — Datasheet Page 19 (p19_fig01)
Datasheet Page 19 (p19_fig01)
P21 · p21_fig011197×1549px
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) — Figure 5: Recommended PCB Land Pattern
Figure 5: Recommended PCB Land Pattern
P21 · p21_fig01P21
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) — Datasheet Page 21 (p21_fig01)
Datasheet Page 21 (p21_fig01)
P22 · p22_fig011031×825px
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) — Figure 6: Module Placement on a Base Board
Figure 6: Module Placement on a Base Board
P22 · p22_fig021381×1117px
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) — Figure 7: Keepout Zone for Module’s Antenna on the Base Board
Figure 7: Keepout Zone for Module’s Antenna on the Base Board
P7 · p07_fig011659×1489px
ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) — 2.1 管脚布局 [QFN-48-EP(7x7)]
2.1 管脚布局 [QFN-48-EP(7x7)]
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (ESP32-PICO-V3-ZERO)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) is a 77-pin wireless wi-fi / bluetooth le soc module featuring a 15.60 × 15.60 × 2.00 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 3.0 ~ 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Wi-Fi, Bluetooth / BLE, UART, SPI interfaces.
Operating Supply VoltageV_CC / V_DD
3.0 ~ 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_TX(peak) ≈ 310 mA @ 3.3V | Deep-Sleep ≈ 10 µA | I_GPIO(max) = 40 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
15.60 × 15.60 × 2.00 mm (A1=0.10 mm)
Package family: OTHER (WIRELM-SMD_ESP32-PICO-V3-ZERO)
Pin Count & Lead PitchN / e
77 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, Bluetooth / BLE, UART, SPI
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol77 auto-grouped pins
OK
IPC-7351B Land Pattern77 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — ESP32-PICO (4)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (WIRELM-SMD_ESP32-PICO-V3-ZERO)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
23.00 × 16.00 mm
Height (A) & Pitch (e)IPC-7351B
A=2.40mm · e=0.80mm
Pad Size (W × L)Level B
0.40 × 0.80 mm
Pins / Total PadsTopology
77P / 77Pad (CASTELLATED_MODULE)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2
BOM
22µF (or 10µF) X5R + 100nF X7R
0805 + 0402
3V3 supply decoupling for ~500mA Wi-Fi TX bursts — place closest to 3V3 pin; supply must deliver >= 600mA.
R_en + C_en
BOM
R = 10kΩ to 3V3 + C = 1µF to GND
0402 / 0603
Power-On Reset RC delay at EN (CHIP_PU) — 1µF capacitor at EN is REQUIRED for reliable cold boot.
R_boot + SW1
BOM
10kΩ Pull-up + BOOT button
0402 + SMD
Firmware boot-mode strap (IO0 on ESP32/S2/S3, IO9 on ESP32-C3) — on C3 pull IO8 high via 10kΩ for UART/USB download.
D_esd
BOM
USBLC6-2SC6 / LESD5D5.0CT1G
SOT-23-6 / SOD-523
ESD surge protection on USB D+/D- — place right next to USB Type-C connector before IO18/IO19/IO20.
ESP32-S3-MINI-1-N8 / 1U-N4R2
Espressif
100% Drop-inSame 15.4×15.4mm 65-pad footprint as ESP32-S2-MINI-2 — verify USB GPIO 19/20 pin mapping.

Technical Frequently Asked Questions (FAQ) — ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO)?

Manufactured by ESPRESSIF, the ESP32-PICO-V3-ZERO is housed in a WIRELM-SMD_ESP32-PICO-V3-ZERO package with 77 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 3.0 ~ 3.6 V. Key pins include: 1 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 2 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 3 (DBG RXD/IO3_: Multiplexed I/O & Peripheral Pin DBG RXD/IO3_ (UART)), 4 (DBG TXD/IO1_: Multiplexed I/O & Peripheral Pin DBG TXD/IO1_ (UART)), 5 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).

What are the IPC-7351B PCB Footprint dimensions for ESP32-PICO-V3-ZERO?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP32-PICO-V3-ZERO (WIRELM-SMD_ESP32-PICO-V3-ZERO) has a nominal body envelope of 16.00 × 23.00 mm, pitch e = 0.80 mm, and 77 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP32-PICO-V3-ZERO?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP32-PICO-V3-ZERO (ESPRESSIF, WIRELM-SMD_ESP32-PICO-V3-ZERO) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (77 pins) & ESP32-PICO Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
2NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
3DBG RXD/IO3_Digital_IOSignal terminal DBG RXD/IO3_ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: UART.
4DBG TXD/IO1_Digital_IOSignal terminal DBG TXD/IO1_ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO1. Supported peripheral buses: UART.
5NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
6NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
7NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
8NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
9NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
10NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
11NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
12NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
13NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
15NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
16NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
17NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
18NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
19ENDigital_IOChip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset.
20GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
21GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
22VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
23GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
24GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
25GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
26GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
27GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
28GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
29GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
30GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
31GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
32GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
33NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
34NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
35NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
36NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
37GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
38NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
39NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
40NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
41U1TXD/IO19Digital_IOSignal terminal U1TXD/IO19 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO19. Supported peripheral buses: UART.
42GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
43VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
44GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
45U1RXD/IO22Digital_IOSignal terminal U1RXD/IO22 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO22. Supported peripheral buses: UART.
46NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
47INT B/IO27_Digital_IOSignal terminal INT B/IO27_ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO27. Supported peripheral buses: General.
48NCNCSignal terminal NC (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
49GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
50GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
51GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
52GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
53GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
54GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
55GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
56GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
57GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
58GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
59GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
60GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
61GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
62GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
63GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
64GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.