SOT-89-3 · 3P
Synchronized Pinout (Symbol / 2D / 3D) (9/9)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | V OUT | I/O | Multiplexed I/O & Peripheral Pin V OUT (General) |
| 2 | VIN | Power | Power Supply Input (VIN — 2.7V to16.0V) |
| 3 | SHDN# | I/O | Multiplexed I/O & Peripheral Pin SHDN# (General) |
| 4 | GND | GND | Ground Reference Pin (GND) |
| 5 | PWRGD | I/O | Multiplexed I/O & Peripheral Pin PWRGD (General) |
| 6 | CDELAY | I/O | Multiplexed I/O & Peripheral Pin CDELAY (General) |
| 7 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 8 | V IN | I/O | Multiplexed I/O & Peripheral Pin V IN (General) |
| 9 | EP | GND | Exposed Thermal & Ground Pad (EP) |
PIN 1 V OUT
I/OMultiplexed I/O & Peripheral Pin V OUT (General)
Design note: RegulatedVoltageOutput
IPC-7351B Solder Density & Span C/G/Z Tuner
Extracted Drawings Gallery (6 Standard Drawings + 10 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (9 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
DFN-8-EP(2x3) · 2.00×3.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (9 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for MCP1703
P1 · p01_fig01377×200px
P1 · p01_fig02P1
P2 · p02_fig011327×1149px
P2 · p02_fig021535×571px
P14 · p14_fig011777×1417px
P14 · p14_fig021777×1540px
P14 · p14_fig01P14
P1 · p01_fig02All Packages in PDF
P17 · p17_fig01All Packages in PDF
P23 · p23_fig01All Packages in PDF
Technical Specifications & Part Details (MCP1703T-4002E/MC)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:MCP1703T-4002E/MC (DFN-8-EP(2x3)) is a 8-pin standard electronic & interconnect component featuring a 3.00 × 2.00 × 0.80 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.7V to16.0V supply operation across -40°C to +125°C with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V to16.0V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +125°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
1 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 2.00 × 0.80 mm (A1=0.03 mm)
Package family: DFN (DFN-8-EP(2x3))
Pin Count & Lead PitchN / e
8 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol9 auto-grouped pins
IPC-7351B Land Pattern9 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteEPAD 1.40×1.30mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — MCP1703 (3)
DFN-8-EP(2x3) · 9P
DFN-8-EP(2x3) · 9P
Mechanical Dimensions & Land Pattern (DFN-8-EP(2x3))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
3.00 × 2.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.80mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.67 mm
Pins / Total PadsTopology
9P / 9Pad (DUAL_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit DFN-8-EP(2x3) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — MCP1703T-4002E/MC (DFN-8-EP(2x3))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of MCP1703T-4002E/MC (DFN-8-EP(2x3))?
Manufactured by MICROCHIP, the MCP1703T-4002E/MC is housed in a DFN-8-EP(2x3) package with 9 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.7V to16.0V. Key pins include: 1 (V OUT: Multiplexed I/O & Peripheral Pin V OUT (General)), 2 (VIN: Power Supply Input (VIN — 2.7V to16.0V)), 3 (SHDN#: Multiplexed I/O & Peripheral Pin SHDN# (General)), 4 (GND: Ground Reference Pin (GND)), 5 (PWRGD: Multiplexed I/O & Peripheral Pin PWRGD (General)), 6 (CDELAY: Multiplexed I/O & Peripheral Pin CDELAY (General)).
What are the IPC-7351B PCB Footprint dimensions for MCP1703T-4002E/MC?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP1703T-4002E/MC (DFN-8-EP(2x3)) has a nominal body envelope of 2.00 × 3.00 mm, pitch e = 0.50 mm, and 9 copper pads plus a central exposed thermal pad (EPAD) of 1.40 × 1.30 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP1703T-4002E/MC?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP1703T-4002E/MC (MICROCHIP, DFN-8-EP(2x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (9 pins) & MCP1703 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | V OUT | Digital_IO | Signal terminal V OUT (I/O, 2.7V to16.0V domain). Multiplexed alternate functions: V OUT. Supported peripheral buses: General. |
| 2 | VIN | Power_In | Primary positive power supply input (VIN) operating in the 2.7V to16.0V domain (Max rating: 16.0V). |
| 3 | SHDN# | Digital_IO | Signal terminal SHDN# (I/O, 2.7V to16.0V domain). Multiplexed alternate functions: SHDN#. Supported peripheral buses: General. |
| 4 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 5 | PWRGD | Digital_IO | Signal terminal PWRGD (I/O, 2.7V to16.0V domain). Multiplexed alternate functions: PWRGD. Supported peripheral buses: General. |
| 6 | CDELAY | Digital_IO | Signal terminal CDELAY (I/O, 2.7V to16.0V domain). Multiplexed alternate functions: CDELAY. Supported peripheral buses: General. |
| 7 | NC | NC | Signal terminal NC (I/O, 2.7V to16.0V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 8 | V IN | Digital_IO | Signal terminal V IN (I/O, 2.7V to16.0V domain). Multiplexed alternate functions: V IN. Supported peripheral buses: General. |
| 9 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |