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C618437 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) — Symbol, Footprint IPC-7351B & 3D STEP Model

C618437

SemiconductorTFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB · 100 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C618437 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)A1VBGA2XINA3XOUTA4PB17A5PB21A6PB23A7TCK/SWCLKA8VDDINA9VDDOUTA10XIN32B1VDDCOREB2GNDUTMIB3VDDUTMIB4PB10B5PB18B6PB24B7NRSTB8TDO/TRACESWOB9TDIB10XOUT32C1DFSDPC2DHSDPC3GNDPLLC4PB14C5PB19C6PB22C7TMS/SWDIOC8NRSTBC9JTAGSELC10VDDBUD1DFSDMD2DHSDMD3VDDPLLD4VDDCORED5PB20D6ERASED7TSTD8FWUPD9PA11/PGMD3D10PA12/PGMD4E1PA29E2GNDE3PA28E4PB9E5GNDBUE6VDDIOE7VDDCOREE8PA10/PGMD2E9PA9/PGMD1E10PA8/PGMD0K10PA25K9PA23/PGMD15K8PA20/PGMD12K7PA17/PGMD9K6PA14/PGMD6K5PB4K4AD12BVREFK3GNDANAK2VDDANAK1PB7J10PA0/PGMNCMDJ9PA26J8PA21/PGMD13J7PA19/PGMD11J6PA16/PGMD8J5PB3J4PA30J3ADVREFJ2PB8J1PB6H10PA2/PGMNOEH9PA1/PGMRDYH8PA24H7PA18/PGMD10H6PA15/PGMD7H5PA13/PGMD5H4PA22/PGMD14H3PA27H2PB5H1VDDCOREG10PA4/PGMM0G9PA5/PGMM1G8PA3/PGMNVALIG7PB15G6GNDG5VDDCOREG4PB13G3PB0G2PB2G1PB11F10PA7/PGMM3F9VDDCOREF8PA6/PGMM2F7PB16F6GNDF5VDDIOF4PA31F3VDDIOF2PB12F1PB1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.268.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1A2A3A4A5A6A7A8A9A10B1B2B3B4B5B6B7B8B9B10C1C2C3C4C5C6C7C8C9C10D1D2D3D4D5D6D7D8D9D10E1E2E3E4E5E6E7E8E9E10F1F2F3F4F5F6F7F8F9F10G1G2G3G4G5G6G7G8G9G10H1H2H3H4H5H6H7H8H9H10J1J2J3J4J5J6J7J8J9J10K1K2K3K4K5K6K7K8K9K10E=9.00mm · Pitch e=0.80mmD=9.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 9.00mm × 9.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VBGI/OMultiplexed I/O & Peripheral Pin VBG (General)
A2XINI/OMultiplexed I/O & Peripheral Pin XIN (RTC/CLK)
A3XOUTI/OMultiplexed I/O & Peripheral Pin XOUT (RTC/CLK)
A4PB17I/OMultiplexed I/O & Peripheral Pin PB17 (General)
A5PB21I/OMultiplexed I/O & Peripheral Pin PB21 (General)
A6PB23I/OMultiplexed I/O & Peripheral Pin PB23 (General)
A7TCK/SWCLKI/OMultiplexed I/O & Peripheral Pin TCK/SWCLK (SWD/JTAG)
A8VDDINPowerPower Supply Input (VDDIN — 3.3V / 5.0V Standard Logic)
A9VDDOUTPowerPower Supply Input (VDDOUT — 3.3V / 5.0V Standard Logic)
A10XIN32I/OMultiplexed I/O & Peripheral Pin XIN32 (RTC/CLK)
B1VDDCOREPowerPower Supply Input (VDDCORE — 3.3V / 5.0V Standard Logic)
B2GNDUTMIGNDGround Reference Pin (GNDUTMI)
B3VDDUTMIPowerPower Supply Input (VDDUTMI — 3.3V / 5.0V Standard Logic)
B4PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
B5PB18I/OMultiplexed I/O & Peripheral Pin PB18 (General)
B6PB24I/OMultiplexed I/O & Peripheral Pin PB24 (General)
B7NRSTISystem Enable & Hardware Reset (NRST)
B8TDO/TRACESWOI/OMultiplexed I/O & Peripheral Pin TDO/TRACESWO (General)
B9TDII/OMultiplexed I/O & Peripheral Pin TDI (General)
B10XOUT32I/OMultiplexed I/O & Peripheral Pin XOUT32 (RTC/CLK)
C1DFSDPI/OMultiplexed I/O & Peripheral Pin DFSDP (General)
C2DHSDPI/OMultiplexed I/O & Peripheral Pin DHSDP (General)
C3GNDPLLGNDGround Reference Pin (GNDPLL)
C4PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
C5PB19I/OMultiplexed I/O & Peripheral Pin PB19 (General)
C6PB22I/OMultiplexed I/O & Peripheral Pin PB22 (General)
C7TMS/SWDIOI/OMultiplexed I/O & Peripheral Pin TMS/SWDIO (SWD/JTAG)
C8NRSTBI/OMultiplexed I/O & Peripheral Pin NRSTB (General)
C9JTAGSELI/OMultiplexed I/O & Peripheral Pin JTAGSEL (SWD/JTAG)
C10VDDBUPowerPower Supply Input (VDDBU — 3.3V / 5.0V Standard Logic)
D1DFSDMI/OMultiplexed I/O & Peripheral Pin DFSDM (General)
D2DHSDMI/OMultiplexed I/O & Peripheral Pin DHSDM (General)
D3VDDPLLPowerPower Supply Input (VDDPLL — 3.3V / 5.0V Standard Logic)
D4VDDCOREPowerPower Supply Input (VDDCORE — 3.3V / 5.0V Standard Logic)
D5PB20I/OMultiplexed I/O & Peripheral Pin PB20 (General)
D6ERASEI/OMultiplexed I/O & Peripheral Pin ERASE (General)
D7TSTI/OMultiplexed I/O & Peripheral Pin TST (General)
D8FWUPI/OMultiplexed I/O & Peripheral Pin FWUP (General)
D9PA11/PGMD3I/OMultiplexed I/O & Peripheral Pin PA11/PGMD3 (General)
D10PA12/PGMD4I/OMultiplexed I/O & Peripheral Pin PA12/PGMD4 (General)
E1PA29I/OMultiplexed I/O & Peripheral Pin PA29 (General)
E2GNDGNDGround Reference Pin (GND)
E3PA28I/OMultiplexed I/O & Peripheral Pin PA28 (General)
E4PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
E5GNDBUGNDGround Reference Pin (GNDBU)
E6VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
E7VDDCOREPowerPower Supply Input (VDDCORE — 3.3V / 5.0V Standard Logic)
E8PA10/PGMD2I/OMultiplexed I/O & Peripheral Pin PA10/PGMD2 (General)
E9PA9/PGMD1I/OMultiplexed I/O & Peripheral Pin PA9/PGMD1 (General)
E10PA8/PGMD0I/OMultiplexed I/O & Peripheral Pin PA8/PGMD0 (General)
F1PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
F2PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
F3VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
F4PA31I/OMultiplexed I/O & Peripheral Pin PA31 (General)
F5VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
F6GNDGNDGround Reference Pin (GND)
F7PB16I/OMultiplexed I/O & Peripheral Pin PB16 (General)
F8PA6/PGMM2I/OMultiplexed I/O & Peripheral Pin PA6/PGMM2 (General)
F9VDDCOREPowerPower Supply Input (VDDCORE — 3.3V / 5.0V Standard Logic)
F10PA7/PGMM3I/OMultiplexed I/O & Peripheral Pin PA7/PGMM3 (General)
G1PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
G2PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
G3PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
G4PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
G5VDDCOREPowerPower Supply Input (VDDCORE — 3.3V / 5.0V Standard Logic)
G6GNDGNDGround Reference Pin (GND)
G7PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
G8PA3/PGMNVALIDI/OMultiplexed I/O & Peripheral Pin PA3/PGMNVALID (General)
G9PA5/PGMM1I/OMultiplexed I/O & Peripheral Pin PA5/PGMM1 (General)
G10PA4/PGMM0I/OMultiplexed I/O & Peripheral Pin PA4/PGMM0 (General)
H1VDDCOREPowerPower Supply Input (VDDCORE — 3.3V / 5.0V Standard Logic)
H2PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
H3PA27I/OMultiplexed I/O & Peripheral Pin PA27 (General)
H4PA22/PGMD14I/OMultiplexed I/O & Peripheral Pin PA22/PGMD14 (General)
H5PA13/PGMD5I/OMultiplexed I/O & Peripheral Pin PA13/PGMD5 (General)
H6PA15/PGMD7I/OMultiplexed I/O & Peripheral Pin PA15/PGMD7 (General)
H7PA18/PGMD10I/OMultiplexed I/O & Peripheral Pin PA18/PGMD10 (General)
H8PA24I/OMultiplexed I/O & Peripheral Pin PA24 (General)
H9PA1/PGMRDYI/OMultiplexed I/O & Peripheral Pin PA1/PGMRDY (General)
H10PA2/PGMNOEI/OMultiplexed I/O & Peripheral Pin PA2/PGMNOE (General)
J1PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
J2PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
J3ADVREFI/OMultiplexed I/O & Peripheral Pin ADVREF (General)
J4PA30I/OMultiplexed I/O & Peripheral Pin PA30 (General)
J5PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
J6PA16/PGMD8I/OMultiplexed I/O & Peripheral Pin PA16/PGMD8 (General)
J7PA19/PGMD11I/OMultiplexed I/O & Peripheral Pin PA19/PGMD11 (General)
J8PA21/PGMD13I/OMultiplexed I/O & Peripheral Pin PA21/PGMD13 (General)
J9PA26I/OMultiplexed I/O & Peripheral Pin PA26 (General)
J10PA0/PGMNCMDI/OMultiplexed I/O & Peripheral Pin PA0/PGMNCMD (General)
K1PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
K2VDDANAPowerPower Supply Input (VDDANA — 3.3V / 5.0V Standard Logic)
K3GNDANAGNDGround Reference Pin (GNDANA)
K4AD12BVREFI/OMultiplexed I/O & Peripheral Pin AD12BVREF (General)
K5PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
K6PA14/PGMD6I/OMultiplexed I/O & Peripheral Pin PA14/PGMD6 (General)
K7PA17/PGMD9I/OMultiplexed I/O & Peripheral Pin PA17/PGMD9 (General)
K8PA20/PGMD12I/OMultiplexed I/O & Peripheral Pin PA20/PGMD12 (General)
K9PA23/PGMD15I/OMultiplexed I/O & Peripheral Pin PA23/PGMD15 (General)
K10PA25I/OMultiplexed I/O & Peripheral Pin PA25 (General)
PIN A1 VBG
I/O
Multiplexed I/O & Peripheral Pin VBG (General)
Design note: Signal terminal VBG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VBG. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C618437 (Semiconductor · TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C618437 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C618437 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C618437 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C618437 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 4. Package Dimensions (D×E×A)
TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB · 9.00×9.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
C618437 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
C618437 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C618437)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C618437 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) is a 100-pin standard electronic & interconnect component featuring a 9.00 × 9.00 × 1.12 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.00 × 9.00 × 1.12 mm (A1=0.25 mm)
Package family: BGA (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.00 × 9.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.12mm · e=0.80mm
Pad Size (W × L)Level B
0.40 × 0.40 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C618437 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C618437 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)?

Manufactured by Semiconductor, the C618437 is housed in a TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB package with 100 pins and a 0.80 mm lead pitch. Key pins include: A1 (VBG: Multiplexed I/O & Peripheral Pin VBG (General)), A2 (XIN: Multiplexed I/O & Peripheral Pin XIN (RTC/CLK)), A3 (XOUT: Multiplexed I/O & Peripheral Pin XOUT (RTC/CLK)), A4 (PB17: Multiplexed I/O & Peripheral Pin PB17 (General)), A5 (PB21: Multiplexed I/O & Peripheral Pin PB21 (General)), A6 (PB23: Multiplexed I/O & Peripheral Pin PB23 (General)).

What are the IPC-7351B PCB Footprint dimensions for C618437?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C618437 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) has a nominal body envelope of 9.00 × 9.00 mm, pitch e = 0.80 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C618437?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C618437 (Semiconductor, TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & C618437 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VBGDigital_IOSignal terminal VBG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VBG. Supported peripheral buses: General.
A2XINDigital_IOSignal terminal XIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XIN. Supported peripheral buses: RTC/CLK.
A3XOUTDigital_IOSignal terminal XOUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XOUT. Supported peripheral buses: RTC/CLK.
A4PB17Digital_IOSignal terminal PB17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB17. Supported peripheral buses: General.
A5PB21Digital_IOSignal terminal PB21 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB21. Supported peripheral buses: General.
A6PB23Digital_IOSignal terminal PB23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB23. Supported peripheral buses: General.
A7TCK/SWCLKDigital_IOSignal terminal TCK/SWCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TCK/SWCLK. Supported peripheral buses: SWD/JTAG.
A8VDDINPower_InPrimary positive power supply input (VDDIN) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
A9VDDOUTPower_InPrimary positive power supply input (VDDOUT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
A10XIN32Digital_IOSignal terminal XIN32 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XIN32. Supported peripheral buses: RTC/CLK.
B1VDDCOREPower_InPrimary positive power supply input (VDDCORE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
B2GNDUTMIGND0V electrical ground return terminal (GNDUTMI) for internal core logic, I/O drivers, and analog sub-blocks.
B3VDDUTMIPower_InPrimary positive power supply input (VDDUTMI) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
B4PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
B5PB18Digital_IOSignal terminal PB18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB18. Supported peripheral buses: General.
B6PB24Digital_IOSignal terminal PB24 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB24. Supported peripheral buses: General.
B7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
B8TDO/TRACESWODigital_IOSignal terminal TDO/TRACESWO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TDO/TRACESWO. Supported peripheral buses: General.
B9TDIDigital_IOSignal terminal TDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TDI. Supported peripheral buses: General.
B10XOUT32Digital_IOSignal terminal XOUT32 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XOUT32. Supported peripheral buses: RTC/CLK.
C1DFSDPDigital_IOSignal terminal DFSDP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFSDP. Supported peripheral buses: General.
C2DHSDPDigital_IOSignal terminal DHSDP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DHSDP. Supported peripheral buses: General.
C3GNDPLLGND0V electrical ground return terminal (GNDPLL) for internal core logic, I/O drivers, and analog sub-blocks.
C4PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
C5PB19Digital_IOSignal terminal PB19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB19. Supported peripheral buses: General.
C6PB22Digital_IOSignal terminal PB22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB22. Supported peripheral buses: General.
C7TMS/SWDIODigital_IOSignal terminal TMS/SWDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TMS/SWDIO. Supported peripheral buses: SWD/JTAG.
C8NRSTBDigital_IOSignal terminal NRSTB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NRSTB. Supported peripheral buses: General.
C9JTAGSELDigital_IOSignal terminal JTAGSEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: JTAGSEL. Supported peripheral buses: SWD/JTAG.
C10VDDBUPower_InPrimary positive power supply input (VDDBU) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
D1DFSDMDigital_IOSignal terminal DFSDM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DFSDM. Supported peripheral buses: General.
D2DHSDMDigital_IOSignal terminal DHSDM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DHSDM. Supported peripheral buses: General.
D3VDDPLLPower_InPrimary positive power supply input (VDDPLL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
D4VDDCOREPower_InPrimary positive power supply input (VDDCORE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
D5PB20Digital_IOSignal terminal PB20 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB20. Supported peripheral buses: General.
D6ERASEDigital_IOSignal terminal ERASE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ERASE. Supported peripheral buses: General.
D7TSTDigital_IOSignal terminal TST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TST. Supported peripheral buses: General.
D8FWUPDigital_IOSignal terminal FWUP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FWUP. Supported peripheral buses: General.
D9PA11/PGMD3Digital_IOSignal terminal PA11/PGMD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/PGMD3. Supported peripheral buses: General.
D10PA12/PGMD4Digital_IOSignal terminal PA12/PGMD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12/PGMD4. Supported peripheral buses: General.
E1PA29Digital_IOSignal terminal PA29 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA29. Supported peripheral buses: General.
E2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
E3PA28Digital_IOSignal terminal PA28 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA28. Supported peripheral buses: General.
E4PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
E5GNDBUGND0V electrical ground return terminal (GNDBU) for internal core logic, I/O drivers, and analog sub-blocks.
E6VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E7VDDCOREPower_InPrimary positive power supply input (VDDCORE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E8PA10/PGMD2Digital_IOSignal terminal PA10/PGMD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10/PGMD2. Supported peripheral buses: General.
E9PA9/PGMD1Digital_IOSignal terminal PA9/PGMD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9/PGMD1. Supported peripheral buses: General.
E10PA8/PGMD0Digital_IOSignal terminal PA8/PGMD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8/PGMD0. Supported peripheral buses: General.
F1PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
F2PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
F3VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
F4PA31Digital_IOSignal terminal PA31 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA31. Supported peripheral buses: General.
F5VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
F6GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
F7PB16Digital_IOSignal terminal PB16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB16. Supported peripheral buses: General.
F8PA6/PGMM2Digital_IOSignal terminal PA6/PGMM2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6/PGMM2. Supported peripheral buses: General.
F9VDDCOREPower_InPrimary positive power supply input (VDDCORE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
F10PA7/PGMM3Digital_IOSignal terminal PA7/PGMM3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7/PGMM3. Supported peripheral buses: General.
G1PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
G2PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
G3PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
G4PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
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