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STM32C011F6U7TR (UFQFPN-20(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32C011F6U7TR

STID: C5909851UFQFPN-20(3x3) · 20 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32C011F6U7TR (UFQFPN-20(3x3))1PC15 - OSCX_2VDD/VDDA3VSS/VSSA4PF2NRST -5PA06PA17PA28PA39PA410PA520PC14 - OSCX_19PB718PB617PA14BOOT0 -16PA1315PA12[PA10]14PA11[PA9]13PA812PA711PA6Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1918171413129874322011615111065E=3.00mm · Pitch e=0.50mmD=3.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PC15 - OSCX_OUT (PC15)I/OMultiplexed I/O & Peripheral Pin PC15 - OSCX_OUT (PC15) (PWM, RTC/CLK)
2VDD/VDDAPowerPower Supply Input (VDD/VDDA — 3.3V VDD (Max 4.0V))
3VSS/VSSAGNDGround Reference Pin (VSS/VSSA)
4PF2NRST -I/OMultiplexed I/O & Peripheral Pin PF2NRST - (RTC/CLK)
5PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC)
6PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, SPI, I2C, ADC)
7PA2I/OMultiplexed I/O & Peripheral Pin PA2 (SPI, ADC, PWM)
8PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
9PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, ADC, PWM, RTC/CLK)
10PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
11PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
12PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
13PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, SPI, ADC, PWM, RTC/CLK)
14PA11[PA9]I/OMultiplexed I/O & Peripheral Pin PA11[PA9] (UART, SPI, ADC)
15PA12[PA10]I/OMultiplexed I/O & Peripheral Pin PA12[PA10] (UART, SPI, ADC)
16PA13I/OMultiplexed I/O & Peripheral Pin PA13 (UART, ADC, SWD/JTAG)
17PA14BOOT0 -I/OMultiplexed I/O & Peripheral Pin PA14BOOT0 - (UART, SPI, ADC, PWM, SWD/JTAG)
18PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
19PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
20PC14 - OSCX_IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSCX_IN (PC14) (UART, I2C, RTC/CLK)
PIN 1 PC15 - OSCX_OUT (PC15)
I/O
Multiplexed I/O & Peripheral Pin PC15 - OSCX_OUT (PC15) (PWM, RTC/CLK)
Design note: Alt: OSC32 EN OSC_ENTIM1ETR ,_ ,_ , TIM3_CH3 | Add: OSCX_OUT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32C011F6U7TR (ST · UFQFPN-20(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32C011F6U7TR (UFQFPN-20(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32C011F6U7TR (UFQFPN-20(3x3)) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32C011F6U7TR (UFQFPN-20(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32C011F6U7TR (UFQFPN-20(3x3)) - 4. Package Dimensions (D×E×A)
UFQFPN-20(3x3) · 3.00×3.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32C011F6U7TR (UFQFPN-20(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32C011F6U7TR (UFQFPN-20(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for STM32C011
P28 · p28_fig01EXACT PACKAGE
STM32C011F6U7TR (UFQFPN-20(3x3)) — Figure 5. STM32C011FxP TSSOP20 pinout
Figure 5. STM32C011FxP TSSOP20 pinout
P28 · p28_fig02EXACT PACKAGE
STM32C011F6U7TR (UFQFPN-20(3x3)) — Figure 6. STM32C011FxU UFQFPN20 pinout
Figure 6. STM32C011FxU UFQFPN20 pinout
P88 · p88_fig02EXACT PACKAGE
STM32C011F6U7TR (UFQFPN-20(3x3)) — Figure 36. UFQFPN20 - Outline D
Figure 36. UFQFPN20 - Outline D
P89 · p89_fig01EXACT PACKAGE
STM32C011F6U7TR (UFQFPN-20(3x3)) — Figure 37. UFQFPN20 - Footprint example
Figure 37. UFQFPN20 - Footprint example
P90 · p90_fig01EXACT PACKAGE
STM32C011F6U7TR (UFQFPN-20(3x3)) — Figure 38. UFQFPN20 package marking example Product identification(1)
Figure 38. UFQFPN20 package marking example Product identification(1)
P1 · p01_fig011225×595px
STM32C011F6U7TR (UFQFPN-20(3x3)) — Arm®Cortex®-M0+ 32-bit MCU, 32 KB Flash, 6 KB RAM, | 2 x USART, timers, ADC, comm. I/Fs, 2-3.6 V | Datasheet - production data | • Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 48 MHz • -40°C to 85°C/105°C/125°C operating temperature •
Arm®Cortex®-M0+ 32-bit MCU, 32 KB Flash, 6 KB RAM, | 2 x USART, timers, ADC, comm. I/Fs, 2-3.6 V | Datasheet - production data | • Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 48 MHz • -40°C to 85°C/105°C/125°C operating temperature •
P28 · p28_fig031678×888px
STM32C011F6U7TR (UFQFPN-20(3x3)) — 28/94 DS13866 Rev 3
28/94 DS13866 Rev 3
P42 · p42_fig011394×1776px
STM32C011F6U7TR (UFQFPN-20(3x3)) — IDD(Run) Supply
IDD(Run) Supply
P43 · p43_fig011394×1836px
STM32C011F6U7TR (UFQFPN-20(3x3)) — STM32C011x4/x6 Electrical characteristics
STM32C011x4/x6 Electrical characteristics
P55 · p55_fig011546×702px
STM32C011F6U7TR (UFQFPN-20(3x3)) — Figure 14. Typical application with an 8 MHz crystal
Figure 14. Typical application with an 8 MHz crystal
P71 · p71_fig011751×1599px
STM32C011F6U7TR (UFQFPN-20(3x3)) — Figure 20. ADC accuracy characteristics (or )] [1LSB =
Figure 20. ADC accuracy characteristics (or )] [1LSB =
P71 · p71_fig01P71
STM32C011F6U7TR (UFQFPN-20(3x3)) — Datasheet Page 71 (p71_fig01)
Datasheet Page 71 (p71_fig01)
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (STM32C011F6U7TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32C011F6U7TR (UFQFPN-20(3x3)) is a 20-pin embedded microcontroller unit (mcu) featuring a 3.00 × 3.00 × 0.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.0 V to 3.6 V supply operation across -40°C to 85°C with integrated UART, SPI, I2C, I2S, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
2.0 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
48 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
15 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.60 mm (A1=0.04 mm)
Package family: QFN (UFQFPN-20(3x3))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PA14BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFQFPN-20(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.00 mm
Pins / Total PadsTopology
20P / 20Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFQFPN-20(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32C011F6U7TR (UFQFPN-20(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32C011F6U7TR (UFQFPN-20(3x3))?

Manufactured by ST, the STM32C011F6U7TR is housed in a UFQFPN-20(3x3) package with 20 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.0 V to 3.6 V. Key pins include: 1 (PC15 - OSCX_OUT (PC15): Multiplexed I/O & Peripheral Pin PC15 - OSCX_OUT (PC15) (PWM, RTC/CLK)), 2 (VDD/VDDA: Power Supply Input (VDD/VDDA — 3.3V VDD (Max 4.0V))), 3 (VSS/VSSA: Ground Reference Pin (VSS/VSSA)), 4 (PF2NRST -: Multiplexed I/O & Peripheral Pin PF2NRST - (RTC/CLK)), 5 (PA0: Multiplexed I/O & Peripheral Pin PA0 (UART, ADC)), 6 (PA1: Multiplexed I/O & Peripheral Pin PA1 (UART, SPI, I2C, ADC)).

What are the IPC-7351B PCB Footprint dimensions for STM32C011F6U7TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32C011F6U7TR (UFQFPN-20(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32C011F6U7TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32C011F6U7TR (ST, UFQFPN-20(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & STM32C011 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PC15 - OSCX_OUT (PC15)Digital_IOSignal terminal PC15 - OSCX_OUT (PC15) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15 - OSCX_OUT (PC15). Supported peripheral buses: PWM, RTC/CLK.
2VDD/VDDAPower_InPrimary positive power supply input (VDD/VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
3VSS/VSSAGND0V electrical ground return terminal (VSS/VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
4PF2NRST -Digital_IOSignal terminal PF2NRST - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2NRST -. Supported peripheral buses: RTC/CLK.
5PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC.
6PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK, I2C1_SMBAEVENTOUT. Supported peripheral buses: UART, SPI, I2C, ADC.
7PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
8PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
9PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI, ADC, PWM, RTC/CLK.
10PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, PWM.
11PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC.
12PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
13PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, PWM, RTC/CLK.
14PA11[PA9]Digital_IOSignal terminal PA11[PA9] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC.
15PA12[PA10]Digital_IOSignal terminal PA12[PA10] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI, ADC.
16PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: UART, ADC, SWD/JTAG.
17PA14BOOT0 -Digital_IOSignal terminal PA14BOOT0 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, PWM, SWD/JTAG.
18PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
19PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
20PC14 - OSCX_IN (PC14)Digital_IOSignal terminal PC14 - OSCX_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSCX_IN (PC14). Supported peripheral buses: UART, I2C, RTC/CLK.
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