ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH422G (SOP-16) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH422G

WCHID: C57543SOP-16 · 16 Pins · Pitch 1.27mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH422G (SOP-16)1IO42IO53IO64IO75SCL6SDA7GND8OC016IO315IO214VCC13IO112IO011OC310OC29OC1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.215.210.25.10-5.1-10.2-15.2mm
2. 2D FOOTPRINT
12345678910111213141516E=3.90mm · Pitch e=1.27mmD=9.90mm-6-5-4-3-2-1012345676543210-1-2-3-4-5-6-7mm
3. 3D CAD MODEL
Package Body: 3.90mm × 9.90mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (16/16)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1IO4I/OMultiplexed I/O & Peripheral Pin IO4 (General)
2IO5I/OMultiplexed I/O & Peripheral Pin IO5 (General)
3IO6I/OMultiplexed I/O & Peripheral Pin IO6 (General)
4IO7I/OMultiplexed I/O & Peripheral Pin IO7 (General)
5SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
6SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
7GNDGNDGround Reference Pin (GND)
8OC0I/OMultiplexed I/O & Peripheral Pin OC0 (General)
9OC1I/OMultiplexed I/O & Peripheral Pin OC1 (General)
10OC2I/OMultiplexed I/O & Peripheral Pin OC2 (General)
11OC3I/OMultiplexed I/O & Peripheral Pin OC3 (General)
12IO0I/OMultiplexed I/O & Peripheral Pin IO0 (General)
13IO1I/OMultiplexed I/O & Peripheral Pin IO1 (General)
14VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
15IO2I/OMultiplexed I/O & Peripheral Pin IO2 (General)
16IO3I/OMultiplexed I/O & Peripheral Pin IO3 (General)
PIN 1 IO4
I/O
Multiplexed I/O & Peripheral Pin IO4 (General)
Design note: Signal terminal IO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO4. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH422G (WCH · SOP-16)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH422G (SOP-16) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH422G (SOP-16) - 2. Standard Pinout (Top View)
True package pinout (16 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH422G (SOP-16) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH422G (SOP-16) - 4. Package Dimensions (D×E×A)
SOP-16 · 3.90×9.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH422G (SOP-16) - 5. Recommended Land Pattern
IPC-7351B Footprint (16 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH422G (SOP-16) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH422
P2 · p02_fig02EXACT PACKAGE
CH422G (SOP-16) — 5.1. Internal Circuit Principle (for function interpretation, for reference only)
5.1. Internal Circuit Principle (for function interpretation, for reference only)
P1 · p01_fig011694×862px
CH422G (SOP-16) — 2. Features
2. Features
P2 · p02_fig01878×364px
CH422G (SOP-16) — Package Width of Plastic Pitch of Pin Instruction of
Package Width of Plastic Pitch of Pin Instruction of
P2 · p02_fig01P2
CH422G (SOP-16) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P2 · p02_fig02P2
CH422G (SOP-16) — Datasheet Page 2 (p02_fig02)
Datasheet Page 2 (p02_fig02)
P8 · p08_fig011344×408px
CH422G (SOP-16) — If a common anode LED nixie tube is required to be driven or the drive current is required to be increased, refer to the methods in the data manual for CH452 chip. | 8.2. Remote I/O Extension CH422 is connected to the external MCU through t
If a common anode LED nixie tube is required to be driven or the drive current is required to be increased, refer to the methods in the data manual for CH452 chip. | 8.2. Remote I/O Extension CH422 is connected to the external MCU through t

Technical Specifications & Part Details (CH422G)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH422G (SOP-16) is a 16-pin standard electronic & interconnect component featuring a 9.90 × 3.90 × 1.50 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
1MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.90 × 3.90 × 1.50 mm (A1=0.15 mm)
Package family: SOP (SOP-16)
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (IO0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol16 auto-grouped pins
OK
IPC-7351B Land Pattern16 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOP-16)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.90 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.50mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.55 mm
Pins / Total PadsTopology
16P / 16Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOP-16
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH422G (SOP-16)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH422G (SOP-16)?

Manufactured by WCH, the CH422G is housed in a SOP-16 package with 16 pins and a 1.27 mm lead pitch. Key pins include: 1 (IO4: Multiplexed I/O & Peripheral Pin IO4 (General)), 2 (IO5: Multiplexed I/O & Peripheral Pin IO5 (General)), 3 (IO6: Multiplexed I/O & Peripheral Pin IO6 (General)), 4 (IO7: Multiplexed I/O & Peripheral Pin IO7 (General)), 5 (SCL: Multiplexed I/O & Peripheral Pin SCL (I2C)), 6 (SDA: Multiplexed I/O & Peripheral Pin SDA (I2C)).

What are the IPC-7351B PCB Footprint dimensions for CH422G?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH422G (SOP-16) has a nominal body envelope of 3.90 × 9.90 mm, pitch e = 1.27 mm, and 16 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH422G?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH422G (WCH, SOP-16) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (16 pins) & CH422 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1IO4Digital_IOSignal terminal IO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO4. Supported peripheral buses: General.
2IO5Digital_IOSignal terminal IO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO5. Supported peripheral buses: General.
3IO6Digital_IOSignal terminal IO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO6. Supported peripheral buses: General.
4IO7Digital_IOSignal terminal IO7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO7. Supported peripheral buses: General.
5SCLDigital_IOSignal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
6SDADigital_IOSignal terminal SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
7GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
8OC0Digital_IOSignal terminal OC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC0. Supported peripheral buses: General.
9OC1Digital_IOSignal terminal OC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC1. Supported peripheral buses: General.
10OC2Digital_IOSignal terminal OC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC2. Supported peripheral buses: General.
11OC3Digital_IOSignal terminal OC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OC3. Supported peripheral buses: General.
12IO0Digital_IOSignal terminal IO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO0. Supported peripheral buses: General.
13IO1Digital_IOSignal terminal IO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO1. Supported peripheral buses: General.
14VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
15IO2Digital_IOSignal terminal IO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO2. Supported peripheral buses: General.
16IO3Digital_IOSignal terminal IO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO3. Supported peripheral buses: General.
ExplorePartsPackagesMFRsUpload