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LAN8831T/Q2A (VQFN-64(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

LAN8831T/Q2A

MICROCHIPID: C5745141VQFN-64(8x8) · 65 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · LAN8831T/Q2A (VQFN-64(8x8))1VDDAH2VDDAH3TXRXP_A4TXRXM_A5VDDAL6VDDAL7TXRXP_B8TXRXM_B9TXRXP_C10TXRXM_C11VDDAL12VDDAL13TXRXP_D14TXRXM_D15VDDAH16IO1817IO818IO1919IO2020VDDIO21IO1022TXD023TXD124TXD225TXD326TXD427TXD528VDD29TXD630TXD731VDDIO32TX ER/GPIO7_33GTX_CLK/TXC65EP64ISET63VDDAL_PLL62XI61XO60LDO_O59TX_CLK58RESET_N57IO5756VDDIO55VDD54INT_N/GPIO553COL/GPIO952MDIO51MDC50CRS/GPIO849RX_CLK/RXC/M48RX_ER47VDDIO46RX_DV/RX_CTL45RXD0/MODE044RXD1/MODE143VDD42RXD2/MODE241RXD3/MODE340VSS539RXD4/RGMII_E38RXD5/PHYAD437RXD6/PHYAD336RXD735VDD34TX_EN/TX_CTLGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.848.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465E=8.00mm · Pitch e=0.40mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (65/65)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDAHPowerPower Supply Input (VDDAH — 3.3V / 5.0V Standard Logic)
2VDDAHPowerPower Supply Input (VDDAH — 3.3V / 5.0V Standard Logic)
3TXRXP_AI/OMultiplexed I/O & Peripheral Pin TXRXP_A (General)
4TXRXM_AI/OMultiplexed I/O & Peripheral Pin TXRXM_A (General)
5VDDALPowerPower Supply Input (VDDAL — 3.3V / 5.0V Standard Logic)
6VDDALPowerPower Supply Input (VDDAL — 3.3V / 5.0V Standard Logic)
7TXRXP_BI/OMultiplexed I/O & Peripheral Pin TXRXP_B (General)
8TXRXM_BI/OMultiplexed I/O & Peripheral Pin TXRXM_B (General)
9TXRXP_CI/OMultiplexed I/O & Peripheral Pin TXRXP_C (General)
10TXRXM_CI/OMultiplexed I/O & Peripheral Pin TXRXM_C (General)
11VDDALPowerPower Supply Input (VDDAL — 3.3V / 5.0V Standard Logic)
12VDDALPowerPower Supply Input (VDDAL — 3.3V / 5.0V Standard Logic)
13TXRXP_DI/OMultiplexed I/O & Peripheral Pin TXRXP_D (General)
14TXRXM_DI/OMultiplexed I/O & Peripheral Pin TXRXM_D (General)
15VDDAHPowerPower Supply Input (VDDAH — 3.3V / 5.0V Standard Logic)
16IO18I/OGPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17IO8I/OGPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1
18IO19I/OGPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19IO20I/OGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
21IO10I/OGPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
23TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
24TXD2I/OMultiplexed I/O & Peripheral Pin TXD2 (UART)
25TXD3I/OMultiplexed I/O & Peripheral Pin TXD3 (UART)
26TXD4I/OMultiplexed I/O & Peripheral Pin TXD4 (UART)
27TXD5I/OMultiplexed I/O & Peripheral Pin TXD5 (UART)
28VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
29TXD6I/OMultiplexed I/O & Peripheral Pin TXD6 (UART)
30TXD7I/OMultiplexed I/O & Peripheral Pin TXD7 (UART)
31VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
32TX ER/GPIO7_I/OMultiplexed I/O & Peripheral Pin TX ER/GPIO7_ (General)
33GTX_CLK/TXCI/OMultiplexed I/O & Peripheral Pin GTX_CLK/TXC (General)
34TX_EN/TX_CTLI/OMultiplexed I/O & Peripheral Pin TX_EN/TX_CTL (General)
35VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
36RXD7I/OMultiplexed I/O & Peripheral Pin RXD7 (UART)
37RXD6/PHYAD3I/OMultiplexed I/O & Peripheral Pin RXD6/PHYAD3 (UART)
38RXD5/PHYAD4I/OMultiplexed I/O & Peripheral Pin RXD5/PHYAD4 (UART)
39RXD4/RGMII_ENI/OMultiplexed I/O & Peripheral Pin RXD4/RGMII_EN (UART)
40VSS5GNDGround Reference Pin (VSS5)
41RXD3/MODE3I/OMultiplexed I/O & Peripheral Pin RXD3/MODE3 (UART)
42RXD2/MODE2I/OMultiplexed I/O & Peripheral Pin RXD2/MODE2 (UART)
43VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
44RXD1/MODE1I/OMultiplexed I/O & Peripheral Pin RXD1/MODE1 (UART)
45RXD0/MODE0I/OMultiplexed I/O & Peripheral Pin RXD0/MODE0 (UART)
46RX_DV/RX_CTL/CLK125_ENI/OMultiplexed I/O & Peripheral Pin RX_DV/RX_CTL/CLK125_EN (General)
47VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
48RX_ERI/OMultiplexed I/O & Peripheral Pin RX_ER (General)
49RX_CLK/RXC/MODE4I/OMultiplexed I/O & Peripheral Pin RX_CLK/RXC/MODE4 (General)
50CRS/GPIO8I/OMultiplexed I/O & Peripheral Pin CRS/GPIO8 (General)
51MDCI/OMultiplexed I/O & Peripheral Pin MDC (General)
52MDIOI/OMultiplexed I/O & Peripheral Pin MDIO (General)
53COL/GPIO9I/OMultiplexed I/O & Peripheral Pin COL/GPIO9 (General)
54INT_N/GPIO5I/OMultiplexed I/O & Peripheral Pin INT_N/GPIO5 (General)
55VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
56VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
57IO57I/OGeneral Purpose Digital I/O Pin IO57
58RESET_NISystem Enable & Hardware Reset (RESET_N)
59TX_CLKI/OMultiplexed I/O & Peripheral Pin TX_CLK (General)
60LDO_OI/OMultiplexed I/O & Peripheral Pin LDO_O (General)
61XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
62XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
63VDDAL_PLLPowerPower Supply Input (VDDAL_PLL — 3.3V / 5.0V Standard Logic)
64ISETI/OMultiplexed I/O & Peripheral Pin ISET (General)
65EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 VDDAH
Power
Power Supply Input (VDDAH — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VDDAH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: LAN8831T/Q2A (MICROCHIP · VQFN-64(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
LAN8831T/Q2A (VQFN-64(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
LAN8831T/Q2A (VQFN-64(8x8)) - 2. Standard Pinout (Top View)
True package pinout (65 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
LAN8831T/Q2A (VQFN-64(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LAN8831T/Q2A (VQFN-64(8x8)) - 4. Package Dimensions (D×E×A)
VQFN-64(8x8) · 8.00×8.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
LAN8831T/Q2A (VQFN-64(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (65 Pads)Expand ›
6. Application SchematicSCHEMATIC
LAN8831T/Q2A (VQFN-64(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for LAN8831
P7 · p07_fig01EXACT PACKAGE
LAN8831T/Q2A (VQFN-64(8x8)) — FIGURE 2-1: SYSTEM BLOCK DIAGRAM
FIGURE 2-1: SYSTEM BLOCK DIAGRAM
P1 · p01_fig01376×200px
LAN8831T/Q2A (VQFN-64(8x8)) — Gigabit Ethernet Transceiver with GMII/MII/
Gigabit Ethernet Transceiver with GMII/MII/
P8 · p08_fig011778×1942px
LAN8831T/Q2A (VQFN-64(8x8)) — FIGURE 3-1: PIN ASSIGNMENTS (TOP VIEW)
FIGURE 3-1: PIN ASSIGNMENTS (TOP VIEW)
P8 · p08_fig01P8
LAN8831T/Q2A (VQFN-64(8x8)) — Datasheet Page 8 (p08_fig01)
Datasheet Page 8 (p08_fig01)
P25 · p25_fig011609×1016px
LAN8831T/Q2A (VQFN-64(8x8)) — FIGURE 5-1: LAN8831 BLOCK DIAGRAM
FIGURE 5-1: LAN8831 BLOCK DIAGRAM
P91 · p91_fig011622×492px
LAN8831T/Q2A (VQFN-64(8x8)) — FIGURE 6-3: RESET_N CONFIGURATION STRAP TIMING
FIGURE 6-3: RESET_N CONFIGURATION STRAP TIMING
P104 · p104_fig011740×831px
LAN8831T/Q2A (VQFN-64(8x8)) — FIGURE 6-16: RESET CIRCUIT WITH MIC826 VOLTAGE SUPERVISOR
FIGURE 6-16: RESET CIRCUIT WITH MIC826 VOLTAGE SUPERVISOR
P104 · p104_fig02645×740px
LAN8831T/Q2A (VQFN-64(8x8)) — FIGURE 6-17: REFERENCE CIRCUITS FOR LED STRAPPING PINS
FIGURE 6-17: REFERENCE CIRCUITS FOR LED STRAPPING PINS
P104 · p104_fig02P104
LAN8831T/Q2A (VQFN-64(8x8)) — Datasheet Page 104 (p104_fig02)
Datasheet Page 104 (p104_fig02)
P106 · p106_fig011360×1253px
LAN8831T/Q2A (VQFN-64(8x8)) — 7.0 PACKAGE OUTLINE
7.0 PACKAGE OUTLINE
P108 · p108_fig011057×1217px
LAN8831T/Q2A (VQFN-64(8x8)) — FIGURE 7-2: 64-LEAD VERY THIN PLASTIC QUAD FLAT, NO LEAD PACKAGE (Q2A) - 8X8X0.9 MM BODY [VQFN] WITH 6.5 MM EXPOSED PAD (DIMENSIONS)
FIGURE 7-2: 64-LEAD VERY THIN PLASTIC QUAD FLAT, NO LEAD PACKAGE (Q2A) - 8X8X0.9 MM BODY [VQFN] WITH 6.5 MM EXPOSED PAD (DIMENSIONS)
P108 · p108_fig01P108
LAN8831T/Q2A (VQFN-64(8x8)) — Datasheet Page 108 (p108_fig01)
Datasheet Page 108 (p108_fig01)
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (LAN8831T/Q2A)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:LAN8831T/Q2A (VQFN-64(8x8)) is a 64-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 0°C to +70°C with integrated RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
0°C to +70°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
125 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (VQFN-64(8x8))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol65 auto-grouped pins
OK
IPC-7351B Land Pattern65 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 6.50×6.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (VQFN-64(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.80 mm
Pins / Total PadsTopology
65P / 65Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
VQFN-64(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — LAN8831T/Q2A (VQFN-64(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of LAN8831T/Q2A (VQFN-64(8x8))?

Manufactured by MICROCHIP, the LAN8831T/Q2A is housed in a VQFN-64(8x8) package with 65 pins and a 0.40 mm lead pitch. Key pins include: 1 (VDDAH: Power Supply Input (VDDAH — 3.3V / 5.0V Standard Logic)), 2 (VDDAH: Power Supply Input (VDDAH — 3.3V / 5.0V Standard Logic)), 3 (TXRXP_A: Multiplexed I/O & Peripheral Pin TXRXP_A (General)), 4 (TXRXM_A: Multiplexed I/O & Peripheral Pin TXRXM_A (General)), 5 (VDDAL: Power Supply Input (VDDAL — 3.3V / 5.0V Standard Logic)), 6 (VDDAL: Power Supply Input (VDDAL — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for LAN8831T/Q2A?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), LAN8831T/Q2A (VQFN-64(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.40 mm, and 65 copper pads plus a central exposed thermal pad (EPAD) of 6.50 × 6.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for LAN8831T/Q2A?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for LAN8831T/Q2A (MICROCHIP, VQFN-64(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (65 pins) & LAN8831 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDAHPower_InPrimary positive power supply input (VDDAH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2VDDAHPower_InPrimary positive power supply input (VDDAH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3TXRXP_ADigital_IOSignal terminal TXRXP_A (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXP_A. Supported peripheral buses: General.
4TXRXM_ADigital_IOSignal terminal TXRXM_A (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXM_A. Supported peripheral buses: General.
5VDDALPower_InPrimary positive power supply input (VDDAL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6VDDALPower_InPrimary positive power supply input (VDDAL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
7TXRXP_BDigital_IOSignal terminal TXRXP_B (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXP_B. Supported peripheral buses: General.
8TXRXM_BDigital_IOSignal terminal TXRXM_B (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXM_B. Supported peripheral buses: General.
9TXRXP_CDigital_IOSignal terminal TXRXP_C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXP_C. Supported peripheral buses: General.
10TXRXM_CDigital_IOSignal terminal TXRXM_C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXM_C. Supported peripheral buses: General.
11VDDALPower_InPrimary positive power supply input (VDDAL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
12VDDALPower_InPrimary positive power supply input (VDDAL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
13TXRXP_DDigital_IOSignal terminal TXRXP_D (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXP_D. Supported peripheral buses: General.
14TXRXM_DDigital_IOSignal terminal TXRXM_D (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXM_D. Supported peripheral buses: General.
15VDDAHPower_InPrimary positive power supply input (VDDAH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
16IO18Digital_IOGPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17IO8Digital_IOGPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1
18IO19Digital_IOGPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19IO20Digital_IOGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21IO10Digital_IOGPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
23TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
24TXD2Digital_IOSignal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART.
25TXD3Digital_IOSignal terminal TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART.
26TXD4Digital_IOSignal terminal TXD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD4. Supported peripheral buses: UART.
27TXD5Digital_IOSignal terminal TXD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD5. Supported peripheral buses: UART.
28VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
29TXD6Digital_IOSignal terminal TXD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD6. Supported peripheral buses: UART.
30TXD7Digital_IOSignal terminal TXD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD7. Supported peripheral buses: UART.
31VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
32TX ER/GPIO7_Digital_IOSignal terminal TX ER/GPIO7_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TX ER/GPIO7_. Supported peripheral buses: General.
33GTX_CLK/TXCDigital_IOSignal terminal GTX_CLK/TXC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GTX_CLK/TXC. Supported peripheral buses: General.
34TX_EN/TX_CTLDigital_IOSignal terminal TX_EN/TX_CTL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TX_EN/TX_CTL. Supported peripheral buses: General.
35VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
36RXD7Digital_IOSignal terminal RXD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD7. Supported peripheral buses: UART.
37RXD6/PHYAD3Digital_IOSignal terminal RXD6/PHYAD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD6/PHYAD3. Supported peripheral buses: UART.
38RXD5/PHYAD4Digital_IOSignal terminal RXD5/PHYAD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD5/PHYAD4. Supported peripheral buses: UART.
39RXD4/RGMII_ENDigital_IOSignal terminal RXD4/RGMII_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD4/RGMII_EN. Supported peripheral buses: UART.
40VSS5GND0V electrical ground return terminal (VSS5) for internal core logic, I/O drivers, and analog sub-blocks.
41RXD3/MODE3Digital_IOSignal terminal RXD3/MODE3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3/MODE3. Supported peripheral buses: UART.
42RXD2/MODE2Digital_IOSignal terminal RXD2/MODE2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2/MODE2. Supported peripheral buses: UART.
43VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
44RXD1/MODE1Digital_IOSignal terminal RXD1/MODE1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1/MODE1. Supported peripheral buses: UART.
45RXD0/MODE0Digital_IOSignal terminal RXD0/MODE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0/MODE0. Supported peripheral buses: UART.
46RX_DV/RX_CTL/CLK125_ENDigital_IOSignal terminal RX_DV/RX_CTL/CLK125_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RX_DV/RX_CTL/CLK125_EN. Supported peripheral buses: General.
47VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
48RX_ERDigital_IOSignal terminal RX_ER (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RX_ER. Supported peripheral buses: General.
49RX_CLK/RXC/MODE4Digital_IOSignal terminal RX_CLK/RXC/MODE4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RX_CLK/RXC/MODE4. Supported peripheral buses: General.
50CRS/GPIO8Digital_IOSignal terminal CRS/GPIO8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CRS/GPIO8. Supported peripheral buses: General.
51MDCDigital_IOSignal terminal MDC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDC. Supported peripheral buses: General.
52MDIODigital_IOSignal terminal MDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIO. Supported peripheral buses: General.
53COL/GPIO9Digital_IOSignal terminal COL/GPIO9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: COL/GPIO9. Supported peripheral buses: General.
54INT_N/GPIO5Digital_IOSignal terminal INT_N/GPIO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT_N/GPIO5. Supported peripheral buses: General.
55VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
56VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
57IO57Digital_IOGeneral Purpose Digital I/O Pin IO57
58RESET_NDigital_IOActive-low hardware reset terminal (RESET_N): pulling this pin Low resets the processor core and peripherals.
59TX_CLKDigital_IOSignal terminal TX_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TX_CLK. Supported peripheral buses: General.
60LDO_ODigital_IOSignal terminal LDO_O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LDO_O. Supported peripheral buses: General.
61XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
62XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
63VDDAL_PLLPower_InPrimary positive power supply input (VDDAL_PLL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
64ISETDigital_IOSignal terminal ISET (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ISET. Supported peripheral buses: General.
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