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CH32F208WBU6 (QFN-68(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32F208WBU6

WCHID: C5711206QFN-68(8x8) · 69 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32F208WBU6 (QFN-68(8x8))1VBAT2PC13 - TAMPE3PC14 - OSC324PC15 - OSC325VSSA6OSC_IN7OSC_OUT8NRST9PC010PC111PC212PC313VDDA14PA0 WKUP -15PA116PA217V_IO418PD419PA320PA421PA522PA623PA724PC425PC526PB027PB128PB229PB1030PB1131V I/O_132VDD_133PD534PD635PB1269VSS68VDD_367V I/O_366PD365PB964PB863BOOT062PB761PB660PB559PB458PB357PD256PC1255PC1154PC1053PA1552PA1451ANT50V INTA49VSS_248PA1347PA1246PA1145PA1044PA943PA842PC941PC840PC739PC638PB1537PB1436PB13Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.850.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869E=8.00mm · Pitch e=0.40mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (69/69)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
2PC13 - TAMPER RTC(2) -I/OMultiplexed I/O & Peripheral Pin PC13 - TAMPER RTC(2) - (RTC/CLK)
3PC14 - OSC32 IN(2)_I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32 IN(2)_ (RTC/CLK)
4PC15 - OSC32 OUT(2)_I/OMultiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(2)_ (RTC/CLK)
5VSSAGNDGround Reference Pin (VSSA)
6OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
7OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
8NRSTISystem Enable & Hardware Reset (NRST)
9PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
10PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
11PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
12PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
13VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
14PA0 WKUP -I/OMultiplexed I/O & Peripheral Pin PA0 WKUP - (UART, ADC, PWM)
15PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
16PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
17V_IO4I/OMultiplexed I/O & Peripheral Pin V_IO4 (General)
18PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
19PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
20PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI)
21PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
22PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
23PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
24PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
25PC5I/OMultiplexed I/O & Peripheral Pin PC5 (ADC)
26PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
27PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
28PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
29PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, I2C)
30PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C)
31V I/O_1I/OMultiplexed I/O & Peripheral Pin V I/O_1 (General)
32VDD_1PowerPower Supply Input (VDD_1 — 3.3V / 5.0V Standard Logic)
33PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
34PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
35PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
36PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
37PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
38PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM)
39PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
40PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
41PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
42PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
43PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
44PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, PWM)
45PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, PWM)
46PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, PWM, CAN)
47PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, CAN)
48PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
49VSS_2GNDExposed Thermal & Ground Pad (VSS_2)
50V INTAI/OMultiplexed I/O & Peripheral Pin V INTA (General)
51ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
52PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
53PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
54PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART)
55PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART)
56PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
57PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
58PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
59PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
60PB5I/OMultiplexed I/O & Peripheral Pin PB5 (I2C)
61PB6I/OMultiplexed I/O & Peripheral Pin PB6 (USB, I2C, PWM)
62PB7I/OMultiplexed I/O & Peripheral Pin PB7 (USB, I2C)
63BOOT0IInput-Only Pin BOOT0 (General)
64PB8I/OMultiplexed I/O & Peripheral Pin PB8 (PWM)
65PB9I/OMultiplexed I/O & Peripheral Pin PB9 (PWM)
66PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
67V I/O_3I/OMultiplexed I/O & Peripheral Pin V I/O_3 (General)
68VDD_3PowerPower Supply Input (VDD_3 — 3.3V / 5.0V Standard Logic)
69VSSGNDGround Reference Pin (VSS)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
Design note: VBAT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32F208WBU6 (WCH · QFN-68(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32F208WBU6 (QFN-68(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32F208WBU6 (QFN-68(8x8)) - 2. Standard Pinout (Top View)
True package pinout (69 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32F208WBU6 (QFN-68(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32F208WBU6 (QFN-68(8x8)) - 4. Package Dimensions (D×E×A)
QFN-68(8x8) · 8.00×8.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32F208WBU6 (QFN-68(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (69 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32F208WBU6 (QFN-68(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for CH32F208
P44 · p44_fig01EXACT PACKAGE
CH32F208WBU6 (QFN-68(8x8)) — Figure 5-1 QFN68X8 package
Figure 5-1 QFN68X8 package
P18 · p18_fig011368×1166px
CH32F208WBU6 (QFN-68(8x8)) — Chapter 3 Pinouts and pin definition
Chapter 3 Pinouts and pin definition
P18 · p18_fig01P18
CH32F208WBU6 (QFN-68(8x8)) — Datasheet Page 18 (p18_fig01)
Datasheet Page 18 (p18_fig01)
P40 · p40_fig011852×1111px
CH32F208WBU6 (QFN-68(8x8)) — The above formula is used to determine the maximum external impedance so that the error can be less than 1/4 LSB. Where N=12 (representing 12-bit resolution). | Table 4-28 Maximum RAIN when fADC = 14MHz | TS(cycle) tS (us) Maximum RAIN(kΩ)
The above formula is used to determine the maximum external impedance so that the error can be less than 1/4 LSB. Where N=12 (representing 12-bit resolution). | Table 4-28 Maximum RAIN when fADC = 14MHz | TS(cycle) tS (us) Maximum RAIN(kΩ)
P40 · p40_fig01P40
CH32F208WBU6 (QFN-68(8x8)) — Datasheet Page 40 (p40_fig01)
Datasheet Page 40 (p40_fig01)
P44 · p44_fig02847×615px
CH32F208WBU6 (QFN-68(8x8)) — Figure 5-2 LQFP64M package
Figure 5-2 LQFP64M package
P44 · p44_fig01P44
CH32F208WBU6 (QFN-68(8x8)) — Datasheet Page 44 (p44_fig01)
Datasheet Page 44 (p44_fig01)

Technical Specifications & Part Details (CH32F208WBU6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH32F208WBU6 (QFN-68(8x8)) is a 68-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, CAN, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
144MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-68(8x8))
Pin Count & Lead PitchN / e
68 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, CAN, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol69 auto-grouped pins
OK
IPC-7351B Land Pattern69 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 6.65×6.65mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-68(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
69P / 69Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-68(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32F208WBU6 (QFN-68(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32F208WBU6 (QFN-68(8x8))?

Manufactured by WCH, the CH32F208WBU6 is housed in a QFN-68(8x8) package with 69 pins and a 0.40 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)), 2 (PC13 - TAMPER RTC(2) -: Multiplexed I/O & Peripheral Pin PC13 - TAMPER RTC(2) - (RTC/CLK)), 3 (PC14 - OSC32 IN(2)_: Multiplexed I/O & Peripheral Pin PC14 - OSC32 IN(2)_ (RTC/CLK)), 4 (PC15 - OSC32 OUT(2)_: Multiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(2)_ (RTC/CLK)), 5 (VSSA: Ground Reference Pin (VSSA)), 6 (OSC_IN: Multiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH32F208WBU6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32F208WBU6 (QFN-68(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.40 mm, and 69 copper pads plus a central exposed thermal pad (EPAD) of 6.65 × 6.65 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32F208WBU6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32F208WBU6 (WCH, QFN-68(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (69 pins) & CH32F208 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2PC13 - TAMPER RTC(2) -Digital_IOSignal terminal PC13 - TAMPER RTC(2) - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13 - TAMPER RTC(2) -. Supported peripheral buses: RTC/CLK.
3PC14 - OSC32 IN(2)_Digital_IOSignal terminal PC14 - OSC32 IN(2)_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14 - OSC32 IN(2)_. Supported peripheral buses: RTC/CLK.
4PC15 - OSC32 OUT(2)_Digital_IOSignal terminal PC15 - OSC32 OUT(2)_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15 - OSC32 OUT(2)_. Supported peripheral buses: RTC/CLK.
5VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
6OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
7OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
8NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
9PC0Digital_IOSignal terminal PC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
10PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
11PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC.
12PC3Digital_IOSignal terminal PC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC.
13VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14PA0 WKUP -Digital_IOSignal terminal PA0 WKUP - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0 WKUP -. Supported peripheral buses: UART, ADC, PWM.
15PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
16PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
17V_IO4Digital_IOSignal terminal V_IO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V_IO4. Supported peripheral buses: General.
18PD4Digital_IOSignal terminal PD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
19PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
20PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI.
21PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC.
22PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC.
23PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC.
24PC4Digital_IOSignal terminal PC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
25PC5Digital_IOSignal terminal PC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC.
26PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
27PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
28PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
29PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: UART, I2C.
30PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: UART, I2C.
31V I/O_1Digital_IOSignal terminal V I/O_1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V I/O_1. Supported peripheral buses: General.
32VDD_1Power_InPrimary positive power supply input (VDD_1) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
33PD5Digital_IOSignal terminal PD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
34PD6Digital_IOSignal terminal PD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
35PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI, I2C.
36PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
37PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, PWM.
38PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, PWM.
39PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
40PC7Digital_IOSignal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
41PC8Digital_IOSignal terminal PC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
42PC9Digital_IOSignal terminal PC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
43PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
44PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, PWM.
45PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART, PWM.
46PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: USB, UART, PWM, CAN.
47PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: USB, UART, CAN.
48PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
49VSS_2GNDBottom exposed die attach pad (VSS_2) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
50V INTADigital_IOSignal terminal V INTA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V INTA. Supported peripheral buses: General.
51ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
52PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
53PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
54PC10Digital_IOSignal terminal PC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC10. Supported peripheral buses: UART.
55PC11Digital_IOSignal terminal PC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC11. Supported peripheral buses: UART.
56PC12Digital_IOSignal terminal PC12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
57PD2Digital_IOSignal terminal PD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
58PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
59PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
60PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C1_SMBA. Supported peripheral buses: I2C.
61PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: USB, I2C, PWM.
62PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: USB, I2C.
63BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
64PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: PWM.
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