ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH450H (SOP-20-300mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH450H

WCHID: C56245SOP-20-300mil · 20 Pins · Pitch 1.27mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH450H (SOP-20-300mil)1DIG32DIG43SCL4SDA5GND6DIG57DIG68DIG79RSTH10SEG020DIG219INT#18SEG717SEG616SEG515SEG414SEG313SEG212VCC11SEG1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=7.50mm · Pitch e=1.27mmD=12.80mm-9-7-5-3-11357997531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 7.50mm × 12.80mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1DIG3I/OMultiplexed I/O & Peripheral Pin DIG3 (General)
2DIG4I/OMultiplexed I/O & Peripheral Pin DIG4 (General)
3SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
4SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
5GNDGNDGround Reference Pin (GND)
6DIG5I/OMultiplexed I/O & Peripheral Pin DIG5 (General)
7DIG6I/OMultiplexed I/O & Peripheral Pin DIG6 (General)
8DIG7I/OMultiplexed I/O & Peripheral Pin DIG7 (General)
9RSTHI/OMultiplexed I/O & Peripheral Pin RSTH (General)
10SEG0I/OMultiplexed I/O & Peripheral Pin SEG0 (General)
11SEG1I/OMultiplexed I/O & Peripheral Pin SEG1 (General)
12VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
13SEG2I/OMultiplexed I/O & Peripheral Pin SEG2 (General)
14SEG3I/OMultiplexed I/O & Peripheral Pin SEG3 (General)
15SEG4I/OMultiplexed I/O & Peripheral Pin SEG4 (General)
16SEG5I/OMultiplexed I/O & Peripheral Pin SEG5 (General)
17SEG6I/OMultiplexed I/O & Peripheral Pin SEG6 (General)
18SEG7I/OMultiplexed I/O & Peripheral Pin SEG7 (General)
19INT#I/OMultiplexed I/O & Peripheral Pin INT# (General)
20DIG2I/OMultiplexed I/O & Peripheral Pin DIG2 (General)
PIN 1 DIG3
I/O
Multiplexed I/O & Peripheral Pin DIG3 (General)
Design note: Signal terminal DIG3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG3. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH450H (WCH · SOP-20-300mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH450H (SOP-20-300mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH450H (SOP-20-300mil) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH450H (SOP-20-300mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH450H (SOP-20-300mil) - 4. Package Dimensions (D×E×A)
SOP-20-300mil · 7.50×12.80mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH450H (SOP-20-300mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH450H (SOP-20-300mil) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (CH450H)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH450H (SOP-20-300mil) is a 20-pin standard electronic & interconnect component featuring a 12.80 × 7.50 × 2.50 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
12.80 × 7.50 × 2.50 mm (A1=0.20 mm)
Package family: SOP (SOP-20-300mil)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOP-20-300mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
12.80 × 7.50 mm
Height (A) & Pitch (e)IPC-7351B
A=2.50mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.90 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOP-20-300mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH450H (SOP-20-300mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH450H (SOP-20-300mil)?

Manufactured by WCH, the CH450H is housed in a SOP-20-300mil package with 20 pins and a 1.27 mm lead pitch. Key pins include: 1 (DIG3: Multiplexed I/O & Peripheral Pin DIG3 (General)), 2 (DIG4: Multiplexed I/O & Peripheral Pin DIG4 (General)), 3 (SCL: Multiplexed I/O & Peripheral Pin SCL (I2C)), 4 (SDA: Multiplexed I/O & Peripheral Pin SDA (I2C)), 5 (GND: Ground Reference Pin (GND)), 6 (DIG5: Multiplexed I/O & Peripheral Pin DIG5 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH450H?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH450H (SOP-20-300mil) has a nominal body envelope of 7.50 × 12.80 mm, pitch e = 1.27 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH450H?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH450H (WCH, SOP-20-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & CH450 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1DIG3Digital_IOSignal terminal DIG3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG3. Supported peripheral buses: General.
2DIG4Digital_IOSignal terminal DIG4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG4. Supported peripheral buses: General.
3SCLDigital_IOSignal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
4SDADigital_IOSignal terminal SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
5GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
6DIG5Digital_IOSignal terminal DIG5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG5. Supported peripheral buses: General.
7DIG6Digital_IOSignal terminal DIG6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG6. Supported peripheral buses: General.
8DIG7Digital_IOSignal terminal DIG7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG7. Supported peripheral buses: General.
9RSTHDigital_IOSignal terminal RSTH (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTH. Supported peripheral buses: General.
10SEG0Digital_IOSignal terminal SEG0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG0. Supported peripheral buses: General.
11SEG1Digital_IOSignal terminal SEG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG1. Supported peripheral buses: General.
12VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
13SEG2Digital_IOSignal terminal SEG2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG2. Supported peripheral buses: General.
14SEG3Digital_IOSignal terminal SEG3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG3. Supported peripheral buses: General.
15SEG4Digital_IOSignal terminal SEG4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG4. Supported peripheral buses: General.
16SEG5Digital_IOSignal terminal SEG5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG5. Supported peripheral buses: General.
17SEG6Digital_IOSignal terminal SEG6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG6. Supported peripheral buses: General.
18SEG7Digital_IOSignal terminal SEG7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG7. Supported peripheral buses: General.
19INT#Digital_IOSignal terminal INT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT#. Supported peripheral buses: General.
20DIG2Digital_IOSignal terminal DIG2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG2. Supported peripheral buses: General.
ExplorePartsPackagesMFRsUpload