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PIC18LF4620-I/P (PDIP-40) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC18LF4620-I/P

MICROCHIPID: C556918PDIP-40 · 40 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC18LF4620-I/P (PDIP-40)1MCLR#/VPP/RE2RA0/AN03RA1/AN14RA2/AN2/VREF5RA3/AN3/VREF6RA4/T0CKI/C17NC8RE0/RD#/AN59RE1/WR#/AN610RE2/CS#/AN711VDD12VSS13OSC1/CLKI/RA14OSC2/CLKO/RA15RC0/T1OSO/T116RC1/T1OSI/CC17RC2/CCP1/P1A18RC3/SCK/SCL19RD0/PSP020RD1/PSP140RB7/KBI3/PGD39RB6/KBI2/PGC38RB5/KBI1/PGM37RB4/KBI0/AN136RB3/AN9/CCP235RB2/INT2/AN834RB1/INT1/AN133RB0/INT0/FLT32VDD31VSS30RD7/PSP7/P1D29RD6/PSP6/P1C28RD5/PSP5/P1B27RD4/PSP426RC7/RX/DT25RC6/TX/CK24RC5/SDO23RC4/SDI/SDA22RD3/PSP321RD2/PSP2Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.830.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940E=13.74mm · Pitch e=2.54mmD=50.26mm-22-20-18-16-14-12-10-8-6-4-2024681012141618202239373533312927252321191715131197531-1-3-5-7-9-11-13-15-17-19-21-23-25-27-29-31-33-35-37-39mm
3. 3D CAD MODEL
Package Body: 13.74mm × 50.26mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (40/40)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1MCLR#/VPP/RE3I/OMultiplexed I/O & Peripheral Pin MCLR#/VPP/RE3 (General)
2RA0/AN0I/OMultiplexed I/O & Peripheral Pin RA0/AN0 (General)
3RA1/AN1I/OMultiplexed I/O & Peripheral Pin RA1/AN1 (General)
4RA2/AN2/VREF-/CVREFAnalogMultiplexed I/O & Peripheral Pin RA2/AN2/VREF-/CVREF (General)
5RA3/AN3/VREF+AnalogMultiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)
6RA4/T0CKI/C1OUTI/OMultiplexed I/O & Peripheral Pin RA4/T0CKI/C1OUT (General)
7NCNCNo Connect (Leave Floating)
8RE0/RD#/AN5I/OMultiplexed I/O & Peripheral Pin RE0/RD#/AN5 (General)
9RE1/WR#/AN6I/OMultiplexed I/O & Peripheral Pin RE1/WR#/AN6 (General)
10RE2/CS#/AN7I/OMultiplexed I/O & Peripheral Pin RE2/CS#/AN7 (General)
11VDDPowerPower Supply Input (VDD — 2.0V to 5.5V)
12VSSGNDGround Reference Pin (VSS)
13OSC1/CLKI/RA7I/OMultiplexed I/O & Peripheral Pin OSC1/CLKI/RA7 (RTC/CLK)
14OSC2/CLKO/RA6I/OMultiplexed I/O & Peripheral Pin OSC2/CLKO/RA6 (RTC/CLK)
15RC0/T1OSO/T13CKII/OMultiplexed I/O & Peripheral Pin RC0/T1OSO/T13CKI (General)
16RC1/T1OSI/CCP2I/OMultiplexed I/O & Peripheral Pin RC1/T1OSI/CCP2 (General)
17RC2/CCP1/P1AI/OMultiplexed I/O & Peripheral Pin RC2/CCP1/P1A (General)
18RC3/SCK/SCLI/OMultiplexed I/O & Peripheral Pin RC3/SCK/SCL (SPI, I2C)
19RD0/PSP0I/OMultiplexed I/O & Peripheral Pin RD0/PSP0 (General)
20RD1/PSP1I/OMultiplexed I/O & Peripheral Pin RD1/PSP1 (General)
21RD2/PSP2I/OMultiplexed I/O & Peripheral Pin RD2/PSP2 (General)
22RD3/PSP3I/OMultiplexed I/O & Peripheral Pin RD3/PSP3 (General)
23RC4/SDI/SDAI/OMultiplexed I/O & Peripheral Pin RC4/SDI/SDA (I2C)
24RC5/SDOI/OMultiplexed I/O & Peripheral Pin RC5/SDO (General)
25RC6/TX/CKI/OMultiplexed I/O & Peripheral Pin RC6/TX/CK (General)
26RC7/RX/DTI/OMultiplexed I/O & Peripheral Pin RC7/RX/DT (General)
27RD4/PSP4I/OMultiplexed I/O & Peripheral Pin RD4/PSP4 (General)
28RD5/PSP5/P1BI/OMultiplexed I/O & Peripheral Pin RD5/PSP5/P1B (General)
29RD6/PSP6/P1CI/OMultiplexed I/O & Peripheral Pin RD6/PSP6/P1C (General)
30RD7/PSP7/P1DI/OMultiplexed I/O & Peripheral Pin RD7/PSP7/P1D (General)
31VSSGNDGround Reference Pin (VSS)
32VDDPowerPower Supply Input (VDD — 2.0V to 5.5V)
33RB0/INT0/FLT0/AN12I/OMultiplexed I/O & Peripheral Pin RB0/INT0/FLT0/AN12 (General)
34RB1/INT1/AN10I/OMultiplexed I/O & Peripheral Pin RB1/INT1/AN10 (General)
35RB2/INT2/AN8I/OMultiplexed I/O & Peripheral Pin RB2/INT2/AN8 (General)
36RB3/AN9/CCP2I/OMultiplexed I/O & Peripheral Pin RB3/AN9/CCP2 (General)
37RB4/KBI0/AN11I/OMultiplexed I/O & Peripheral Pin RB4/KBI0/AN11 (General)
38RB5/KBI1/PGMI/OMultiplexed I/O & Peripheral Pin RB5/KBI1/PGM (General)
39RB6/KBI2/PGCI/OMultiplexed I/O & Peripheral Pin RB6/KBI2/PGC (General)
40RB7/KBI3/PGDI/OMultiplexed I/O & Peripheral Pin RB7/KBI3/PGD (General)
PIN 1 MCLR#/VPP/RE3
I/O
Multiplexed I/O & Peripheral Pin MCLR#/VPP/RE3 (General)
Design note: Signal terminal MCLR#/VPP/RE3 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: MCLR#/VPP/RE3. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC18LF4620-I/P (MICROCHIP · PDIP-40)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC18LF4620-I/P (PDIP-40) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC18LF4620-I/P (PDIP-40) - 2. Standard Pinout (Top View)
True package pinout (40 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC18LF4620-I/P (PDIP-40) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC18LF4620-I/P (PDIP-40) - 4. Package Dimensions (D×E×A)
PDIP-40 · 13.74×50.26mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC18LF4620-I/P (PDIP-40) - 5. Recommended Land Pattern
IPC-7351B Footprint (40 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC18LF4620-I/P (PDIP-40) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for PIC18LF4620
P2 · p02_fig011777×1640px
PIC18LF4620-I/P (PDIP-40) — DS39626E-page ii © 2008 Microchip Technology Inc. | Trademarks | FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporate
DS39626E-page ii © 2008 Microchip Technology Inc. | Trademarks | FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporate
P2 · p02_fig02788×285px
PIC18LF4620-I/P (PDIP-40) — DS39626E-page ii © 2008 Microchip Technology Inc.
DS39626E-page ii © 2008 Microchip Technology Inc.
P143 · p143_fig011777×345px
PIC18LF4620-I/P (PDIP-40) — FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
P143 · p143_fig021777×1051px
PIC18LF4620-I/P (PDIP-40) — FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
P144 · p144_fig011537×941px
PIC18LF4620-I/P (PDIP-40) — FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM
FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM
P167 · p167_fig011777×937px
PIC18LF4620-I/P (PDIP-40) — FIGURE 17-2: SPI MASTER/SLAVE CONNECTION
FIGURE 17-2: SPI MASTER/SLAVE CONNECTION
P168 · p168_fig011777×1598px
PIC18LF4620-I/P (PDIP-40) — FIGURE 17-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 SCK (CKP = 0
FIGURE 17-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 SCK (CKP = 0
P170 · p170_fig011756×1059px
PIC18LF4620-I/P (PDIP-40) — FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS SCK (CKP = 0 SCK (CKP = 1 CKE = 0) Write to SSPBUF
FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS SCK (CKP = 0 SCK (CKP = 1 CKE = 0) Write to SSPBUF
P170 · p170_fig021777×1097px
PIC18LF4620-I/P (PDIP-40) — FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS SCK (CKP = 0 SCK (CKP = 1 CKE = 1) Write to SSPBUF
FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS SCK (CKP = 0 SCK (CKP = 1 CKE = 1) Write to SSPBUF
P170 · p170_fig01P170
PIC18LF4620-I/P (PDIP-40) — Datasheet Page 170 (p170_fig01)
Datasheet Page 170 (p170_fig01)
P385 · p385_fig021371×652px
PIC18LF4620-I/P (PDIP-40) — Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. | 3 e | 3 e
Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. | 3 e | 3 e
P385 · p385_fig02P385
PIC18LF4620-I/P (PDIP-40) — Datasheet Page 385 (p385_fig02)
Datasheet Page 385 (p385_fig02)
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (PIC18LF4620-I/P)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC18LF4620-I/P (PDIP-40) is a 40-pin standard electronic & interconnect component featuring a 50.26 × 13.74 × 4.20 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 2.0V to 5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.0V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
50.26 × 13.74 × 4.20 mm (A1=0.51 mm)
Package family: DIP (PDIP-40)
Pin Count & Lead PitchN / e
40 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol40 auto-grouped pins
OK
IPC-7351B Land Pattern40 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIP-40)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
50.26 × 13.74 mm
Height (A) & Pitch (e)IPC-7351B
A=4.20mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
40P / 40Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PDIP-40
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC18LF4620-I/P (PDIP-40)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC18LF4620-I/P (PDIP-40)?

Manufactured by MICROCHIP, the PIC18LF4620-I/P is housed in a PDIP-40 package with 40 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (MCLR#/VPP/RE3: Multiplexed I/O & Peripheral Pin MCLR#/VPP/RE3 (General)), 2 (RA0/AN0: Multiplexed I/O & Peripheral Pin RA0/AN0 (General)), 3 (RA1/AN1: Multiplexed I/O & Peripheral Pin RA1/AN1 (General)), 4 (RA2/AN2/VREF-/CVREF: Multiplexed I/O & Peripheral Pin RA2/AN2/VREF-/CVREF (General)), 5 (RA3/AN3/VREF+: Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)), 6 (RA4/T0CKI/C1OUT: Multiplexed I/O & Peripheral Pin RA4/T0CKI/C1OUT (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC18LF4620-I/P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC18LF4620-I/P (PDIP-40) has a nominal body envelope of 13.74 × 50.26 mm, pitch e = 2.54 mm, and 40 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC18LF4620-I/P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC18LF4620-I/P (MICROCHIP, PDIP-40) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (40 pins) & PIC18LF4620 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1MCLR#/VPP/RE3Digital_IOSignal terminal MCLR#/VPP/RE3 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: MCLR#/VPP/RE3. Supported peripheral buses: General.
2RA0/AN0Digital_IOSignal terminal RA0/AN0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA0/AN0. Supported peripheral buses: General.
3RA1/AN1Digital_IOSignal terminal RA1/AN1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA1/AN1. Supported peripheral buses: General.
4RA2/AN2/VREF-/CVREFAnalogSignal terminal RA2/AN2/VREF-/CVREF (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA2/AN2/VREF-/CVREF. Supported peripheral buses: General.
5RA3/AN3/VREF+AnalogSignal terminal RA3/AN3/VREF+ (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA3/AN3/VREF+. Supported peripheral buses: General.
6RA4/T0CKI/C1OUTDigital_IOSignal terminal RA4/T0CKI/C1OUT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA4/T0CKI/C1OUT. Supported peripheral buses: General.
7NCNo_ConnectNo Connect (Leave Floating)
8RE0/RD#/AN5Digital_IOSignal terminal RE0/RD#/AN5 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE0/RD#/AN5. Supported peripheral buses: General.
9RE1/WR#/AN6Digital_IOSignal terminal RE1/WR#/AN6 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE1/WR#/AN6. Supported peripheral buses: General.
10RE2/CS#/AN7Digital_IOSignal terminal RE2/CS#/AN7 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE2/CS#/AN7. Supported peripheral buses: General.
11VDDPower_InPrimary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
12VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
13OSC1/CLKI/RA7Digital_IOSignal terminal OSC1/CLKI/RA7 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC1/CLKI/RA7. Supported peripheral buses: RTC/CLK.
14OSC2/CLKO/RA6Digital_IOSignal terminal OSC2/CLKO/RA6 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC2/CLKO/RA6. Supported peripheral buses: RTC/CLK.
15RC0/T1OSO/T13CKIDigital_IOSignal terminal RC0/T1OSO/T13CKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC0/T1OSO/T13CKI. Supported peripheral buses: General.
16RC1/T1OSI/CCP2Digital_IOSignal terminal RC1/T1OSI/CCP2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC1/T1OSI/CCP2. Supported peripheral buses: General.
17RC2/CCP1/P1ADigital_IOSignal terminal RC2/CCP1/P1A (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC2/CCP1/P1A. Supported peripheral buses: General.
18RC3/SCK/SCLDigital_IOSignal terminal RC3/SCK/SCL (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC3/SCK/SCL. Supported peripheral buses: SPI, I2C.
19RD0/PSP0Digital_IOSignal terminal RD0/PSP0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD0/PSP0. Supported peripheral buses: General.
20RD1/PSP1Digital_IOSignal terminal RD1/PSP1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD1/PSP1. Supported peripheral buses: General.
21RD2/PSP2Digital_IOSignal terminal RD2/PSP2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD2/PSP2. Supported peripheral buses: General.
22RD3/PSP3Digital_IOSignal terminal RD3/PSP3 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD3/PSP3. Supported peripheral buses: General.
23RC4/SDI/SDADigital_IOSignal terminal RC4/SDI/SDA (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC4/SDI/SDA. Supported peripheral buses: I2C.
24RC5/SDODigital_IOSignal terminal RC5/SDO (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC5/SDO. Supported peripheral buses: General.
25RC6/TX/CKDigital_IOSignal terminal RC6/TX/CK (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC6/TX/CK. Supported peripheral buses: General.
26RC7/RX/DTDigital_IOSignal terminal RC7/RX/DT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC7/RX/DT. Supported peripheral buses: General.
27RD4/PSP4Digital_IOSignal terminal RD4/PSP4 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD4/PSP4. Supported peripheral buses: General.
28RD5/PSP5/P1BDigital_IOSignal terminal RD5/PSP5/P1B (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD5/PSP5/P1B. Supported peripheral buses: General.
29RD6/PSP6/P1CDigital_IOSignal terminal RD6/PSP6/P1C (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD6/PSP6/P1C. Supported peripheral buses: General.
30RD7/PSP7/P1DDigital_IOSignal terminal RD7/PSP7/P1D (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD7/PSP7/P1D. Supported peripheral buses: General.
31VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32VDDPower_InPrimary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
33RB0/INT0/FLT0/AN12Digital_IOSignal terminal RB0/INT0/FLT0/AN12 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB0/INT0/FLT0/AN12. Supported peripheral buses: General.
34RB1/INT1/AN10Digital_IOSignal terminal RB1/INT1/AN10 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB1/INT1/AN10. Supported peripheral buses: General.
35RB2/INT2/AN8Digital_IOSignal terminal RB2/INT2/AN8 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB2/INT2/AN8. Supported peripheral buses: General.
36RB3/AN9/CCP2Digital_IOSignal terminal RB3/AN9/CCP2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB3/AN9/CCP2. Supported peripheral buses: General.
37RB4/KBI0/AN11Digital_IOSignal terminal RB4/KBI0/AN11 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB4/KBI0/AN11. Supported peripheral buses: General.
38RB5/KBI1/PGMDigital_IOSignal terminal RB5/KBI1/PGM (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB5/KBI1/PGM. Supported peripheral buses: General.
39RB6/KBI2/PGCDigital_IOSignal terminal RB6/KBI2/PGC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB6/KBI2/PGC. Supported peripheral buses: General.
40RB7/KBI3/PGDDigital_IOSignal terminal RB7/KBI3/PGD (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB7/KBI3/PGD. Supported peripheral buses: General.
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