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CH637X (QFN-88(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH637X

WCHID: C55509536QFN-88(10x10) · 89 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH637X (QFN-88(10x10))1PWR_CC22PWR_CC13SMBCLK/SCL4SMBDAT/SDA5SUSP/SDA2/EX6P7_HS_DP7P7_HS_DM8VBUS_DET9VIO3310PWREN1#11OVCUR1#12PWREN2#13OVCUR2#14VIO3315LED_A1/BC_EN16LED_A2/GANG_17LED_A3/HPD_E18LED_A4/EXCH_19LED_A5/SDA3/20LED_A6/2UP_E21LED_A7/HPD22VDD1223P5_HS_DP24P5_HS_DM25P5_SS_TXB26P5_SS_TXA27P5_VDD1228P5_SS_RXB29P5_SS_RXA30P4_HS_DP31P4_HS_DM32P4_SS_TXB33P4_SS_TXA34P4_VDD1235P4_SS_RXB36P4_SS_RXA37P3_HS_DP38P3_HS_DM39P3_SS_TXB40P3_SS_TXA41P3_SS_RXB42P3_SS_RXA43P3C_SS_RXA44P3C_SS_RXB45P3_VDD1289GND88VDD3387RESET#86P3_CC185P3_CC284HUB_CC183HUB_CC282P6_HS_DM81P6_HS_DP80P6_SS_RXA79P6_SS_RXB78P6_VDD1277P6_SS_TXA76P6_SS_TXB75UP_HS_DM74UP_HS_DP73XO72XI71VDD1270UPC_SS_TXB69UPC_SS_TXA68UPC_SS_RXB67UPC_SS_RXA66UP_SS_RXA65UP_SS_RXB64UP_VDD1263UP_SS_TXA62UP_SS_TXB61P1_SS_RXA60P1_SS_RXB59P1_VDD1258P1_SS_TXA57P1_SS_TXB56P1_HS_DM55P1_HS_DP54P2_SS_RXA53P2_SS_RXB52P2_VDD1251P2_SS_TXA50P2_SS_TXB49P2_HS_DM48P2_HS_DP47P3C_SS_TXB46P3C_SS_TXAGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.263.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889E=10.00mm · Pitch e=0.40mmD=10.00mm-8-6-4-20246886420-2-4-6-8mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (89/89)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PWR_CC2I/OMultiplexed I/O & Peripheral Pin PWR_CC2 (General)
2PWR_CC1I/OMultiplexed I/O & Peripheral Pin PWR_CC1 (General)
3SMBCLK/SCLI/OMultiplexed I/O & Peripheral Pin SMBCLK/SCL (I2C)
4SMBDAT/SDAI/OMultiplexed I/O & Peripheral Pin SMBDAT/SDA (I2C)
5SUSP/SDA2/EXCH#I/OMultiplexed I/O & Peripheral Pin SUSP/SDA2/EXCH# (I2C)
6P7_HS_DPI/OMultiplexed I/O & Peripheral Pin P7_HS_DP (General)
7P7_HS_DMI/OMultiplexed I/O & Peripheral Pin P7_HS_DM (General)
8VBUS_DETPowerPower Supply Input (VBUS_DET — 3.3V / 5.0V Standard Logic)
9VIO33I/OMultiplexed I/O & Peripheral Pin VIO33 (General)
10PWREN1#I/OMultiplexed I/O & Peripheral Pin PWREN1# (General)
11OVCUR1#I/OMultiplexed I/O & Peripheral Pin OVCUR1# (General)
12PWREN2#I/OMultiplexed I/O & Peripheral Pin PWREN2# (General)
13OVCUR2#I/OMultiplexed I/O & Peripheral Pin OVCUR2# (General)
14VIO33I/OMultiplexed I/O & Peripheral Pin VIO33 (General)
15LED_A1/BC_EN#I/OMultiplexed I/O & Peripheral Pin LED_A1/BC_EN# (General)
16LED_A2/GANG_EN#I/OMultiplexed I/O & Peripheral Pin LED_A2/GANG_EN# (General)
17LED_A3/HPD_EN#/2UP_SW#I/OMultiplexed I/O & Peripheral Pin LED_A3/HPD_EN#/2UP_SW# (General)
18LED_A4/EXCH_EN#I/OMultiplexed I/O & Peripheral Pin LED_A4/EXCH_EN# (General)
19LED_A5/SDA3/P45C_EN#I/OMultiplexed I/O & Peripheral Pin LED_A5/SDA3/P45C_EN# (I2C)
20LED_A6/2UP_EN#I/OMultiplexed I/O & Peripheral Pin LED_A6/2UP_EN# (General)
21LED_A7/HPDI/OMultiplexed I/O & Peripheral Pin LED_A7/HPD (General)
22VDD12PowerPower Supply Input (VDD12 — 3.3V / 5.0V Standard Logic)
23P5_HS_DPI/OMultiplexed I/O & Peripheral Pin P5_HS_DP (General)
24P5_HS_DMI/OMultiplexed I/O & Peripheral Pin P5_HS_DM (General)
25P5_SS_TXBI/OMultiplexed I/O & Peripheral Pin P5_SS_TXB (General)
26P5_SS_TXAI/OMultiplexed I/O & Peripheral Pin P5_SS_TXA (General)
27P5_VDD12PowerPower Supply Input (P5_VDD12 — 3.3V / 5.0V Standard Logic)
28P5_SS_RXBI/OMultiplexed I/O & Peripheral Pin P5_SS_RXB (General)
29P5_SS_RXAI/OMultiplexed I/O & Peripheral Pin P5_SS_RXA (General)
30P4_HS_DPI/OMultiplexed I/O & Peripheral Pin P4_HS_DP (General)
31P4_HS_DMI/OMultiplexed I/O & Peripheral Pin P4_HS_DM (General)
32P4_SS_TXBI/OMultiplexed I/O & Peripheral Pin P4_SS_TXB (General)
33P4_SS_TXAI/OMultiplexed I/O & Peripheral Pin P4_SS_TXA (General)
34P4_VDD12PowerPower Supply Input (P4_VDD12 — 3.3V / 5.0V Standard Logic)
35P4_SS_RXBI/OMultiplexed I/O & Peripheral Pin P4_SS_RXB (General)
36P4_SS_RXAI/OMultiplexed I/O & Peripheral Pin P4_SS_RXA (General)
37P3_HS_DPI/OMultiplexed I/O & Peripheral Pin P3_HS_DP (General)
38P3_HS_DMI/OMultiplexed I/O & Peripheral Pin P3_HS_DM (General)
39P3_SS_TXBI/OMultiplexed I/O & Peripheral Pin P3_SS_TXB (General)
40P3_SS_TXAI/OMultiplexed I/O & Peripheral Pin P3_SS_TXA (General)
41P3_SS_RXBI/OMultiplexed I/O & Peripheral Pin P3_SS_RXB (General)
42P3_SS_RXAI/OMultiplexed I/O & Peripheral Pin P3_SS_RXA (General)
43P3C_SS_RXAI/OMultiplexed I/O & Peripheral Pin P3C_SS_RXA (General)
44P3C_SS_RXBI/OMultiplexed I/O & Peripheral Pin P3C_SS_RXB (General)
45P3_VDD12PowerPower Supply Input (P3_VDD12 — 3.3V / 5.0V Standard Logic)
46P3C_SS_TXAI/OMultiplexed I/O & Peripheral Pin P3C_SS_TXA (General)
47P3C_SS_TXBI/OMultiplexed I/O & Peripheral Pin P3C_SS_TXB (General)
48P2_HS_DPI/OMultiplexed I/O & Peripheral Pin P2_HS_DP (General)
49P2_HS_DMI/OMultiplexed I/O & Peripheral Pin P2_HS_DM (General)
50P2_SS_TXBI/OMultiplexed I/O & Peripheral Pin P2_SS_TXB (General)
51P2_SS_TXAI/OMultiplexed I/O & Peripheral Pin P2_SS_TXA (General)
52P2_VDD12PowerPower Supply Input (P2_VDD12 — 3.3V / 5.0V Standard Logic)
53P2_SS_RXBI/OMultiplexed I/O & Peripheral Pin P2_SS_RXB (General)
54P2_SS_RXAI/OMultiplexed I/O & Peripheral Pin P2_SS_RXA (General)
55P1_HS_DPI/OMultiplexed I/O & Peripheral Pin P1_HS_DP (General)
56P1_HS_DMI/OMultiplexed I/O & Peripheral Pin P1_HS_DM (General)
57P1_SS_TXBI/OMultiplexed I/O & Peripheral Pin P1_SS_TXB (General)
58P1_SS_TXAI/OMultiplexed I/O & Peripheral Pin P1_SS_TXA (General)
59P1_VDD12PowerPower Supply Input (P1_VDD12 — 3.3V / 5.0V Standard Logic)
60P1_SS_RXBI/OMultiplexed I/O & Peripheral Pin P1_SS_RXB (General)
61P1_SS_RXAI/OMultiplexed I/O & Peripheral Pin P1_SS_RXA (General)
62UP_SS_TXBI/OMultiplexed I/O & Peripheral Pin UP_SS_TXB (General)
63UP_SS_TXAI/OMultiplexed I/O & Peripheral Pin UP_SS_TXA (General)
64UP_VDD12PowerPower Supply Input (UP_VDD12 — 3.3V / 5.0V Standard Logic)
65UP_SS_RXBI/OMultiplexed I/O & Peripheral Pin UP_SS_RXB (General)
66UP_SS_RXAI/OMultiplexed I/O & Peripheral Pin UP_SS_RXA (General)
67UPC_SS_RXAI/OMultiplexed I/O & Peripheral Pin UPC_SS_RXA (General)
68UPC_SS_RXBI/OMultiplexed I/O & Peripheral Pin UPC_SS_RXB (General)
69UPC_SS_TXAI/OMultiplexed I/O & Peripheral Pin UPC_SS_TXA (General)
70UPC_SS_TXBI/OMultiplexed I/O & Peripheral Pin UPC_SS_TXB (General)
71VDD12PowerPower Supply Input (VDD12 — 3.3V / 5.0V Standard Logic)
72XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
73XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
74UP_HS_DPI/OMultiplexed I/O & Peripheral Pin UP_HS_DP (General)
75UP_HS_DMI/OMultiplexed I/O & Peripheral Pin UP_HS_DM (General)
76P6_SS_TXBI/OMultiplexed I/O & Peripheral Pin P6_SS_TXB (General)
77P6_SS_TXAI/OMultiplexed I/O & Peripheral Pin P6_SS_TXA (General)
78P6_VDD12PowerPower Supply Input (P6_VDD12 — 3.3V / 5.0V Standard Logic)
79P6_SS_RXBI/OMultiplexed I/O & Peripheral Pin P6_SS_RXB (General)
80P6_SS_RXAI/OMultiplexed I/O & Peripheral Pin P6_SS_RXA (General)
81P6_HS_DPI/OMultiplexed I/O & Peripheral Pin P6_HS_DP (General)
82P6_HS_DMI/OMultiplexed I/O & Peripheral Pin P6_HS_DM (General)
83HUB_CC2I/OMultiplexed I/O & Peripheral Pin HUB_CC2 (General)
84HUB_CC1I/OMultiplexed I/O & Peripheral Pin HUB_CC1 (General)
85P3_CC2I/OMultiplexed I/O & Peripheral Pin P3_CC2 (General)
86P3_CC1I/OMultiplexed I/O & Peripheral Pin P3_CC1 (General)
87RESET#ISystem Enable & Hardware Reset (RESET#)
88VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
89GNDGNDGround Reference Pin (GND)
PIN 1 PWR_CC2
I/O
Multiplexed I/O & Peripheral Pin PWR_CC2 (General)
Design note: Signal terminal PWR_CC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWR_CC2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH637X (WCH · QFN-88(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH637X (QFN-88(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH637X (QFN-88(10x10)) - 2. Standard Pinout (Top View)
True package pinout (89 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH637X (QFN-88(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH637X (QFN-88(10x10)) - 4. Package Dimensions (D×E×A)
QFN-88(10x10) · 10.00×10.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH637X (QFN-88(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (89 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH637X (QFN-88(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for CH637
P5 · p05_fig01EXACT PACKAGE
CH637X (QFN-88(10x10)) — V1.1 5
V1.1 5
P1 · p01_fig011743×1191px
CH637X (QFN-88(10x10)) — 图1-1 系统框图
图1-1 系统框图
P4 · p04_fig011545×2644px
CH637X (QFN-88(10x10)) — V1.1 4
V1.1 4
P4 · p04_fig01P4
CH637X (QFN-88(10x10)) — Datasheet Page 4 (p04_fig01)
Datasheet Page 4 (p04_fig01)
P26 · p26_fig011724×2276px
CH637X (QFN-88(10x10)) — 图8-1 CH637X 芯片7 口HUB 参考电路图 VDD12 UP_SS_TXA P1_HS_DM 56
图8-1 CH637X 芯片7 口HUB 参考电路图 VDD12 UP_SS_TXA P1_HS_DM 56
P26 · p26_fig01P26
CH637X (QFN-88(10x10)) — Datasheet Page 26 (p26_fig01)
Datasheet Page 26 (p26_fig01)
P28 · p28_fig011689×2452px
CH637X (QFN-88(10x10)) — 图8-2 CH637X 芯片多Type-C 接口参考电路图 VDD12 UP_SS_RXA UP_SS_RXA 66
图8-2 CH637X 芯片多Type-C 接口参考电路图 VDD12 UP_SS_RXA UP_SS_RXA 66

Technical Specifications & Part Details (CH637X)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH637X (QFN-88(10x10)) is a 88-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, I2C, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-88(10x10))
Pin Count & Lead PitchN / e
88 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, I2C, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol89 auto-grouped pins
OK
IPC-7351B Land Pattern89 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 5.70×5.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-88(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
89P / 89Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-88(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH637X (QFN-88(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH637X (QFN-88(10x10))?

Manufactured by WCH, the CH637X is housed in a QFN-88(10x10) package with 89 pins and a 0.40 mm lead pitch. Key pins include: 1 (PWR_CC2: Multiplexed I/O & Peripheral Pin PWR_CC2 (General)), 2 (PWR_CC1: Multiplexed I/O & Peripheral Pin PWR_CC1 (General)), 3 (SMBCLK/SCL: Multiplexed I/O & Peripheral Pin SMBCLK/SCL (I2C)), 4 (SMBDAT/SDA: Multiplexed I/O & Peripheral Pin SMBDAT/SDA (I2C)), 5 (SUSP/SDA2/EXCH#: Multiplexed I/O & Peripheral Pin SUSP/SDA2/EXCH# (I2C)), 6 (P7_HS_DP: Multiplexed I/O & Peripheral Pin P7_HS_DP (General)).

What are the IPC-7351B PCB Footprint dimensions for CH637X?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH637X (QFN-88(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.40 mm, and 89 copper pads plus a central exposed thermal pad (EPAD) of 5.70 × 5.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH637X?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH637X (WCH, QFN-88(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (89 pins) & CH637 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PWR_CC2Digital_IOSignal terminal PWR_CC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWR_CC2. Supported peripheral buses: General.
2PWR_CC1Digital_IOSignal terminal PWR_CC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWR_CC1. Supported peripheral buses: General.
3SMBCLK/SCLDigital_IOSignal terminal SMBCLK/SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SMBCLK/SCL. Supported peripheral buses: I2C.
4SMBDAT/SDADigital_IOSignal terminal SMBDAT/SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SMBDAT/SDA. Supported peripheral buses: I2C.
5SUSP/SDA2/EXCH#Digital_IOSignal terminal SUSP/SDA2/EXCH# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SUSP/SDA2/EXCH#. Supported peripheral buses: I2C.
6P7_HS_DPDigital_IOSignal terminal P7_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P7_HS_DP. Supported peripheral buses: General.
7P7_HS_DMDigital_IOSignal terminal P7_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P7_HS_DM. Supported peripheral buses: General.
8VBUS_DETPower_InPrimary positive power supply input (VBUS_DET) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9VIO33Digital_IOSignal terminal VIO33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO33. Supported peripheral buses: General.
10PWREN1#Digital_IOSignal terminal PWREN1# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN1#. Supported peripheral buses: General.
11OVCUR1#Digital_IOSignal terminal OVCUR1# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR1#. Supported peripheral buses: General.
12PWREN2#Digital_IOSignal terminal PWREN2# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN2#. Supported peripheral buses: General.
13OVCUR2#Digital_IOSignal terminal OVCUR2# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR2#. Supported peripheral buses: General.
14VIO33Digital_IOSignal terminal VIO33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO33. Supported peripheral buses: General.
15LED_A1/BC_EN#Digital_IOSignal terminal LED_A1/BC_EN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_A1/BC_EN#. Supported peripheral buses: General.
16LED_A2/GANG_EN#Digital_IOSignal terminal LED_A2/GANG_EN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_A2/GANG_EN#. Supported peripheral buses: General.
17LED_A3/HPD_EN#/2UP_SW#Digital_IOSignal terminal LED_A3/HPD_EN#/2UP_SW# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_A3/HPD_EN#/2UP_SW#. Supported peripheral buses: General.
18LED_A4/EXCH_EN#Digital_IOSignal terminal LED_A4/EXCH_EN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_A4/EXCH_EN#. Supported peripheral buses: General.
19LED_A5/SDA3/P45C_EN#Digital_IOSignal terminal LED_A5/SDA3/P45C_EN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_A5/SDA3/P45C_EN#. Supported peripheral buses: I2C.
20LED_A6/2UP_EN#Digital_IOSignal terminal LED_A6/2UP_EN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_A6/2UP_EN#. Supported peripheral buses: General.
21LED_A7/HPDDigital_IOSignal terminal LED_A7/HPD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_A7/HPD. Supported peripheral buses: General.
22VDD12Power_InPrimary positive power supply input (VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
23P5_HS_DPDigital_IOSignal terminal P5_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5_HS_DP. Supported peripheral buses: General.
24P5_HS_DMDigital_IOSignal terminal P5_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5_HS_DM. Supported peripheral buses: General.
25P5_SS_TXBDigital_IOSignal terminal P5_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5_SS_TXB. Supported peripheral buses: General.
26P5_SS_TXADigital_IOSignal terminal P5_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5_SS_TXA. Supported peripheral buses: General.
27P5_VDD12Power_InPrimary positive power supply input (P5_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
28P5_SS_RXBDigital_IOSignal terminal P5_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5_SS_RXB. Supported peripheral buses: General.
29P5_SS_RXADigital_IOSignal terminal P5_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5_SS_RXA. Supported peripheral buses: General.
30P4_HS_DPDigital_IOSignal terminal P4_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_HS_DP. Supported peripheral buses: General.
31P4_HS_DMDigital_IOSignal terminal P4_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_HS_DM. Supported peripheral buses: General.
32P4_SS_TXBDigital_IOSignal terminal P4_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_TXB. Supported peripheral buses: General.
33P4_SS_TXADigital_IOSignal terminal P4_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_TXA. Supported peripheral buses: General.
34P4_VDD12Power_InPrimary positive power supply input (P4_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
35P4_SS_RXBDigital_IOSignal terminal P4_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_RXB. Supported peripheral buses: General.
36P4_SS_RXADigital_IOSignal terminal P4_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_RXA. Supported peripheral buses: General.
37P3_HS_DPDigital_IOSignal terminal P3_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_HS_DP. Supported peripheral buses: General.
38P3_HS_DMDigital_IOSignal terminal P3_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_HS_DM. Supported peripheral buses: General.
39P3_SS_TXBDigital_IOSignal terminal P3_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_TXB. Supported peripheral buses: General.
40P3_SS_TXADigital_IOSignal terminal P3_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_TXA. Supported peripheral buses: General.
41P3_SS_RXBDigital_IOSignal terminal P3_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_RXB. Supported peripheral buses: General.
42P3_SS_RXADigital_IOSignal terminal P3_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_RXA. Supported peripheral buses: General.
43P3C_SS_RXADigital_IOSignal terminal P3C_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3C_SS_RXA. Supported peripheral buses: General.
44P3C_SS_RXBDigital_IOSignal terminal P3C_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3C_SS_RXB. Supported peripheral buses: General.
45P3_VDD12Power_InPrimary positive power supply input (P3_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
46P3C_SS_TXADigital_IOSignal terminal P3C_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3C_SS_TXA. Supported peripheral buses: General.
47P3C_SS_TXBDigital_IOSignal terminal P3C_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3C_SS_TXB. Supported peripheral buses: General.
48P2_HS_DPDigital_IOSignal terminal P2_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_HS_DP. Supported peripheral buses: General.
49P2_HS_DMDigital_IOSignal terminal P2_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_HS_DM. Supported peripheral buses: General.
50P2_SS_TXBDigital_IOSignal terminal P2_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_TXB. Supported peripheral buses: General.
51P2_SS_TXADigital_IOSignal terminal P2_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_TXA. Supported peripheral buses: General.
52P2_VDD12Power_InPrimary positive power supply input (P2_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
53P2_SS_RXBDigital_IOSignal terminal P2_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_RXB. Supported peripheral buses: General.
54P2_SS_RXADigital_IOSignal terminal P2_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_RXA. Supported peripheral buses: General.
55P1_HS_DPDigital_IOSignal terminal P1_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_HS_DP. Supported peripheral buses: General.
56P1_HS_DMDigital_IOSignal terminal P1_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_HS_DM. Supported peripheral buses: General.
57P1_SS_TXBDigital_IOSignal terminal P1_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_TXB. Supported peripheral buses: General.
58P1_SS_TXADigital_IOSignal terminal P1_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_TXA. Supported peripheral buses: General.
59P1_VDD12Power_InPrimary positive power supply input (P1_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
60P1_SS_RXBDigital_IOSignal terminal P1_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_RXB. Supported peripheral buses: General.
61P1_SS_RXADigital_IOSignal terminal P1_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_RXA. Supported peripheral buses: General.
62UP_SS_TXBDigital_IOSignal terminal UP_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_SS_TXB. Supported peripheral buses: General.
63UP_SS_TXADigital_IOSignal terminal UP_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_SS_TXA. Supported peripheral buses: General.
64UP_VDD12Power_InPrimary positive power supply input (UP_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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