Mechanical Dimensions & Land Pattern (DFN-10(3x3))
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit DFN-10(3x3) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH2024Q (DFN-10(3x3))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH2024Q (DFN-10(3x3))?
Manufactured by WCH, the CH2024Q is housed in a DFN-10(3x3) package with 11 pins and a 0.50 mm lead pitch. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (FB: Multiplexed I/O & Peripheral Pin FB (General)), 5 (AGND: Ground Reference Pin (AGND)), 6 (BST: Multiplexed I/O & Peripheral Pin BST (General)).
What are the IPC-7351B PCB Footprint dimensions for CH2024Q?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH2024Q (DFN-10(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 11 copper pads plus a central exposed thermal pad (EPAD) of 2.40 × 1.70 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH2024Q?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH2024Q (WCH, DFN-10(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (11 pins) & CH2024 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | IO1 | Digital_IO | General Purpose Digital I/O Pin IO1 |
| 2 | IO2 | Digital_IO | General Purpose Digital I/O Pin IO2 |
| 3 | 3V3 | Power_In | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | FB | Digital_IO | Signal terminal FB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FB. Supported peripheral buses: General. |
| 5 | AGND | GND | 0V electrical ground return terminal (AGND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 6 | BST | Digital_IO | Signal terminal BST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BST. Supported peripheral buses: General. |
| 7 | SW | Digital_IO | Signal terminal SW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SW. Supported peripheral buses: General. |
| 8 | SW | Digital_IO | Signal terminal SW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SW. Supported peripheral buses: General. |
| 9 | VIN | Power_In | Primary positive power supply input (VIN) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 10 | VIN | Power_In | Primary positive power supply input (VIN) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 11 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |