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CH2003V (SOT-23-6) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH2003V

WCHID: C54973762SOT-23-6 · 6 Pins · Pitch 0.95mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH2003V (SOT-23-6)1NC2GND3SW6FB1V235LDO_3V34VIN5Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.210.25.10-5.1-10.2mm
2. 2D FOOTPRINT
123456E=2.90mm · Pitch e=0.95mmD=1.60mm-3-2-1012343210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 2.90mm × 1.60mm · Pitch: 0.95mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (6/6)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1NCI/OMultiplexed I/O & Peripheral Pin NC (General)
2GNDGNDGround Reference Pin (GND)
3SWI/OMultiplexed I/O & Peripheral Pin SW (General)
4VIN5PowerPower Supply Input (VIN5 — 3.3V / 5.0V Standard Logic)
5LDO_3V3PowerPower Supply Input (LDO_3V3 — 3.3V / 5.0V Standard Logic)
6FB1V23I/OMultiplexed I/O & Peripheral Pin FB1V23 (General)
PIN 1 NC
I/O
Multiplexed I/O & Peripheral Pin NC (General)
Design note: Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH2003V (WCH · SOT-23-6)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH2003V (SOT-23-6) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH2003V (SOT-23-6) - 2. Standard Pinout (Top View)
True package pinout (6 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH2003V (SOT-23-6) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH2003V (SOT-23-6) - 4. Package Dimensions (D×E×A)
SOT-23-6 · 2.90×1.60mm · Pitch 0.95mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH2003V (SOT-23-6) - 5. Recommended Land Pattern
IPC-7351B Footprint (6 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH2003V (SOT-23-6) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH2003
P2 · p02_fig01EXACT PACKAGE
CH2003V (SOT-23-6) — 引脚号 引脚 名称 类型 功能描述 CH2003K CH2003V CH2003W
引脚号 引脚 名称 类型 功能描述 CH2003K CH2003V CH2003W
P2 · p02_fig02EXACT PACKAGE
CH2003V (SOT-23-6) — 封装形式 塑体尺寸 引脚节距 封装说明 订货型号 SOT23-6L 1.6*2.9mm 0.95mm 37mil 小型6 脚贴片 CH2003K SOT23-6L 1.6*2.9mm 0.95mm 37mil 小型6 脚贴片 CH2003V SOT23-6L 1.6*2.9mm 0.95mm 37mil 小型6 脚贴片 CH2003W
封装形式 塑体尺寸 引脚节距 封装说明 订货型号 SOT23-6L 1.6*2.9mm 0.95mm 37mil 小型6 脚贴片 CH2003K SOT23-6L 1.6*2.9mm 0.95mm 37mil 小型6 脚贴片 CH2003V SOT23-6L 1.6*2.9mm 0.95mm 37mil 小型6 脚贴片 CH2003W
P3 · p03_fig011338×573px
CH2003V (SOT-23-6) — 图5-1 CH2003K 典型应用方案示意图
图5-1 CH2003K 典型应用方案示意图
P3 · p03_fig01P3
CH2003V (SOT-23-6) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P4 · p04_fig011268×579px
CH2003V (SOT-23-6) — 图5-2 CH2003V 典型应用方案示意图
图5-2 CH2003V 典型应用方案示意图
P4 · p04_fig021268×579px
CH2003V (SOT-23-6) — 图5-3 CH2003W 典型应用方案示意图
图5-3 CH2003W 典型应用方案示意图
P5 · p05_fig011771×635px
CH2003V (SOT-23-6) — 6.2 CH2003K 电气参数（测试条件：TA = 25℃，VIN5 = 5V，R1 = 200KΩ）
6.2 CH2003K 电气参数（测试条件：TA = 25℃，VIN5 = 5V，R1 = 200KΩ）
P5 · p05_fig021759×1557px
CH2003V (SOT-23-6) — 6.2 CH2003K 电气参数（测试条件：TA = 25℃，VIN5 = 5V，R1 = 200KΩ）
6.2 CH2003K 电气参数（测试条件：TA = 25℃，VIN5 = 5V，R1 = 200KΩ）

Technical Specifications & Part Details (CH2003V)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH2003V (SOT-23-6) is a 6-pin standard electronic & interconnect component featuring a 2.90 × 1.60 × 1.10 mm mechanical envelope (lead pitch e = 0.95 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
5MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
2.90 × 1.60 × 1.10 mm (A1=0.08 mm)
Package family: SOT23 (SOT-23-6)
Pin Count & Lead PitchN / e
6 Pins | Pitch e = 0.95 mm (37.4 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol6 auto-grouped pins
OK
IPC-7351B Land Pattern6 pads · Pitch 0.95mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOT-23-6)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.90 × 1.60 mm
Height (A) & Pitch (e)IPC-7351B
A=1.10mm · e=0.95mm
Pad Size (W × L)Level B
0.60 × 1.00 mm
Pins / Total PadsTopology
6P / 6Pad (SOT_SMALL)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOT-23-6
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH2003V (SOT-23-6)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH2003V (SOT-23-6)?

Manufactured by WCH, the CH2003V is housed in a SOT-23-6 package with 6 pins and a 0.95 mm lead pitch. Key pins include: 1 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 2 (GND: Ground Reference Pin (GND)), 3 (SW: Multiplexed I/O & Peripheral Pin SW (General)), 4 (VIN5: Power Supply Input (VIN5 — 3.3V / 5.0V Standard Logic)), 5 (LDO_3V3: Power Supply Input (LDO_3V3 — 3.3V / 5.0V Standard Logic)), 6 (FB1V23: Multiplexed I/O & Peripheral Pin FB1V23 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH2003V?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH2003V (SOT-23-6) has a nominal body envelope of 1.60 × 2.90 mm, pitch e = 0.95 mm, and 6 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH2003V?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH2003V (WCH, SOT-23-6) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (6 pins) & CH2003 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3SWDigital_IOSignal terminal SW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SW. Supported peripheral buses: General.
4VIN5Power_InPrimary positive power supply input (VIN5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
5LDO_3V3Power_InPrimary positive power supply input (LDO_3V3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6FB1V23Digital_IOSignal terminal FB1V23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FB1V23. Supported peripheral buses: General.
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