QFN-16(2x2) · 16P
Synchronized Pinout (Symbol / 2D / 3D) (16/16)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | IO1 | I/O | General Purpose Digital I/O Pin IO1 |
| 2 | IO2 | I/O | General Purpose Digital I/O Pin IO2 |
| 3 | 3V3 | Power | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | NC | NC | No Connect (Leave Floating) |
| 5 | IO2 | I/O | GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1 |
| 6 | IO3 | I/O | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | VDD | Power | Power Supply Input (VDD — 3.3V / 5.0V Standard Logic) |
| 8 | VBUS | Power | Power Supply Input (VBUS — 3.3V / 5.0V Standard Logic) |
| 9 | IO4 | I/O | GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3 |
| 10 | IO5 | I/O | GPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4 |
| 11 | IO6 | I/O | GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5 |
| 12 | IO7 | I/O | GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6 |
| 13 | CC1 | I/O | Multiplexed I/O & Peripheral Pin CC1 (General) |
| 14 | CC2 | I/O | Multiplexed I/O & Peripheral Pin CC2 (General) |
| 15 | IO17 | I/O | GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6 |
| 16 | IO18 | I/O | GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3 |
PIN 1 IO1
I/OGeneral Purpose Digital I/O Pin IO1
Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (16 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN-16(2x2) · 2.00×2.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (16 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH9441
P4 · p04_fig02EXACT PACKAGE
P7 · p07_fig01EXACT PACKAGE
P7 · p07_fig02EXACT PACKAGE
P1 · p01_fig011557×1370px
P2 · p02_fig011748×2082px
P4 · p04_fig011001×889px
P5 · p05_fig011725×2308px
P5 · p05_fig01P5
Technical Specifications & Part Details (CH9441C)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH9441C (QFN-16(2x2)) is a 16-pin standard electronic & interconnect component featuring a 2.00 × 2.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
2.00 × 2.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-16(2x2))
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol16 auto-grouped pins
IPC-7351B Land Pattern16 pads · Pitch 0.40mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH9441 (2)
QFN-16(3x3) · 17P
Mechanical Dimensions & Land Pattern (QFN-16(2x2))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
2.00 × 2.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.30 mm
Pins / Total PadsTopology
16P / 16Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-16(2x2) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH9441C (QFN-16(2x2))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH9441C (QFN-16(2x2))?
Manufactured by WCH, the CH9441C is housed in a QFN-16(2x2) package with 16 pins and a 0.40 mm lead pitch. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).
What are the IPC-7351B PCB Footprint dimensions for CH9441C?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9441C (QFN-16(2x2)) has a nominal body envelope of 2.00 × 2.00 mm, pitch e = 0.40 mm, and 16 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9441C?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9441C (WCH, QFN-16(2x2)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (16 pins) & CH9441 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | IO1 | Digital_IO | General Purpose Digital I/O Pin IO1 |
| 2 | IO2 | Digital_IO | General Purpose Digital I/O Pin IO2 |
| 3 | 3V3 | Power_In | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | NC | No_Connect | No Connect (Leave Floating) |
| 5 | IO2 | Digital_IO | GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1 |
| 6 | IO3 | Digital_IO | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 8 | VBUS | Power_In | Primary positive power supply input (VBUS) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 9 | IO4 | Digital_IO | GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3 |
| 10 | IO5 | Digital_IO | GPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4 |
| 11 | IO6 | Digital_IO | GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5 |
| 12 | IO7 | Digital_IO | GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6 |
| 13 | CC1 | Digital_IO | Signal terminal CC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CC1. Supported peripheral buses: General. |
| 14 | CC2 | Digital_IO | Signal terminal CC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CC2. Supported peripheral buses: General. |
| 15 | IO17 | Digital_IO | GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6 |
| 16 | IO18 | Digital_IO | GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3 |