QFN-20(2.5x4.5) · 21P
Synchronized Pinout (Symbol / 2D / 3D) (21/21)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | EN# | I/O | Multiplexed I/O & Peripheral Pin EN# (General) |
| 2 | IO2 | I/O | General Purpose Digital I/O Pin IO2 |
| 3 | 3V3 | Power | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | GND | GND | Ground Reference Pin (GND) |
| 5 | VDD | Power | Power Supply Input (VDD — 3.3V / 5.0V Standard Logic) |
| 6 | IO3 | I/O | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | NC | NC | No Connect (Leave Floating) |
| 8 | SEL | I/O | Multiplexed I/O & Peripheral Pin SEL (General) |
| 9 | VDD | Power | Power Supply Input (VDD — 3.3V / 5.0V Standard Logic) |
| 10 | GND | GND | Ground Reference Pin (GND) |
| 11 | IO6 | I/O | GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5 |
| 12 | IO7 | I/O | GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6 |
| 13 | IO15 | I/O | GPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P |
| 14 | IO16 | I/O | GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N |
| 15 | IO17 | I/O | GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6 |
| 16 | IO18 | I/O | GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3 |
| 17 | IO8 | I/O | GPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1 |
| 18 | IO19 | I/O | GPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8 |
| 19 | GND | GND | Ground Reference Pin (GND) |
| 20 | VDD | Power | Power Supply Input (VDD — 3.3V / 5.0V Standard Logic) |
| 21 | GND | GND | Ground Reference Pin (GND) |
PIN 1 EN#
I/OMultiplexed I/O & Peripheral Pin EN# (General)
Design note: 全局使能输入 低电平有效 高电平断开且下电 ， ；
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN-20(2.5x4.5) · 2.50×4.50mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH481 / CH482
P12 · p12_fig01EXACT PACKAGE
P1 · p01_fig01245×132px
P2 · p02_fig011712×2596px
P2 · p02_fig01P2
P5 · p05_fig011729×2546px
P12 · p12_fig01P12
P13 · p13_fig011704×2518px
P14 · p14_fig011701×1868px
Technical Specifications & Part Details (CH481D)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH481D (QFN-20(2.5x4.5)) is a 20-pin standard electronic & interconnect component featuring a 2.50 × 4.50 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
1MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
2.50 × 4.50 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-20(2.5x4.5))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol21 auto-grouped pins
IPC-7351B Land Pattern21 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteEPAD 3.00×1.00mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH481 / CH482 (2)
QFN-20(2.5x4.5) · 21P
Mechanical Dimensions & Land Pattern (QFN-20(2.5x4.5))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
4.50 × 2.50 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.67 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-20(2.5x4.5) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH481D (QFN-20(2.5x4.5))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH481D (QFN-20(2.5x4.5))?
Manufactured by WCH, the CH481D is housed in a QFN-20(2.5x4.5) package with 21 pins and a 0.50 mm lead pitch. Key pins include: 1 (EN#: Multiplexed I/O & Peripheral Pin EN# (General)), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (GND: Ground Reference Pin (GND)), 5 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).
What are the IPC-7351B PCB Footprint dimensions for CH481D?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH481D (QFN-20(2.5x4.5)) has a nominal body envelope of 2.50 × 4.50 mm, pitch e = 0.50 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 3.00 × 1.00 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH481D?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH481D (WCH, QFN-20(2.5x4.5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (21 pins) & CH481 / CH482 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | EN# | Digital_IO | Signal terminal EN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EN#. Supported peripheral buses: General. |
| 2 | IO2 | Digital_IO | General Purpose Digital I/O Pin IO2 |
| 3 | 3V3 | Power_In | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 5 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 6 | IO3 | Digital_IO | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | NC | No_Connect | No Connect (Leave Floating) |
| 8 | SEL | Digital_IO | Signal terminal SEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEL. Supported peripheral buses: General. |
| 9 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 10 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 11 | IO6 | Digital_IO | GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5 |
| 12 | IO7 | Digital_IO | GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6 |
| 13 | IO15 | Digital_IO | GPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P |
| 14 | IO16 | Digital_IO | GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N |
| 15 | IO17 | Digital_IO | GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6 |
| 16 | IO18 | Digital_IO | GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3 |
| 17 | IO8 | Digital_IO | GPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1 |
| 18 | IO19 | Digital_IO | GPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8 |
| 19 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 20 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 21 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |