Mechanical Dimensions & Land Pattern (QFN-16(3x3))
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-16(3x3) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH9441P (QFN-16(3x3))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH9441P (QFN-16(3x3))?
Manufactured by WCH, the CH9441P is housed in a QFN-16(3x3) package with 17 pins and a 0.50 mm lead pitch. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).
What are the IPC-7351B PCB Footprint dimensions for CH9441P?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9441P (QFN-16(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 17 copper pads plus a central exposed thermal pad (EPAD) of 1.80 × 1.80 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9441P?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9441P (WCH, QFN-16(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (17 pins) & CH9441 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | IO1 | Digital_IO | General Purpose Digital I/O Pin IO1 |
| 2 | IO2 | Digital_IO | General Purpose Digital I/O Pin IO2 |
| 3 | 3V3 | Power_In | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | NC | No_Connect | No Connect (Leave Floating) |
| 5 | IO2 | Digital_IO | GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1 |
| 6 | IO3 | Digital_IO | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 8 | VBUS | Power_In | Primary positive power supply input (VBUS) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 9 | IO4 | Digital_IO | GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3 |
| 10 | IO5 | Digital_IO | GPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4 |
| 11 | IO6 | Digital_IO | GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5 |
| 12 | IO7 | Digital_IO | GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6 |
| 13 | CC1 | Digital_IO | Signal terminal CC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CC1. Supported peripheral buses: General. |
| 14 | CC2 | Digital_IO | Signal terminal CC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CC2. Supported peripheral buses: General. |
| 15 | IO17 | Digital_IO | GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6 |
| 16 | IO18 | Digital_IO | GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3 |
| 17 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |