![ESP32-C6 (QFN-40-EP(5x5)) — DIMENSIONS (MM) [-]](/api/v1/assets/C20554022/extracted/pinout_diagram.png)
- · 32P
Synchronized Pinout (Symbol / 2D / 3D) (41/41)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | ANT | I/O | Multiplexed I/O & Peripheral Pin ANT (General) |
| 2 | VDDA3P3 | Power | Power Supply Input (VDDA3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V)) |
| 3 | VDDA3P3 | Power | Power Supply Input (VDDA3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V)) |
| 4 | CHIP_PU | I | System Enable & Hardware Reset (CHIP_PU) |
| 5 | VDDPST1 | Power | Power Supply Input (VDDPST1 — 3.3V VDD3P3 (3.0V ~ 3.6V)) |
| 6 | XTAL_32K_P | I/O | Multiplexed I/O & Peripheral Pin XTAL_32K_P (RTC/CLK) |
| 7 | XTAL_32K_N | I/O | Multiplexed I/O & Peripheral Pin XTAL_32K_N (RTC/CLK) |
| 8 | GPIO2 | I/O | Multiplexed I/O & Peripheral Pin GPIO2 (General) |
| 9 | GPIO3 | I/O | Multiplexed I/O & Peripheral Pin GPIO3 (General) |
| 10 | MTMS | I/O | Multiplexed I/O & Peripheral Pin MTMS (SWD/JTAG) |
| 11 | MTDI | I/O | Multiplexed I/O & Peripheral Pin MTDI (SWD/JTAG) |
| 12 | MTCK | I/O | Multiplexed I/O & Peripheral Pin MTCK (SWD/JTAG) |
| 13 | MTDO | I/O | Multiplexed I/O & Peripheral Pin MTDO (SWD/JTAG) |
| 14 | GPIO8 | I/O | Multiplexed I/O & Peripheral Pin GPIO8 (General) |
| 15 | GPIO9 | I/O | Multiplexed I/O & Peripheral Pin GPIO9 (General) |
| 16 | GPIO10 | I/O | Multiplexed I/O & Peripheral Pin GPIO10 (General) |
| 17 | GPIO11 | I/O | Multiplexed I/O & Peripheral Pin GPIO11 (General) |
| 18 | GPIO12 | I/O | Multiplexed I/O & Peripheral Pin GPIO12 (General) |
| 19 | GPIO13 | I/O | Multiplexed I/O & Peripheral Pin GPIO13 (General) |
| 20 | SPICS0 | I/O | Multiplexed I/O & Peripheral Pin SPICS0 (SPI) |
| 21 | SPIQ | I/O | Multiplexed I/O & Peripheral Pin SPIQ (SPI) |
| 22 | SPIWP | I/O | Multiplexed I/O & Peripheral Pin SPIWP (SPI) |
| 23 | VDD_SPI | Power | Regulated Power Output (VDD_SPI — 3.3V VDD3P3 (3.0V ~ 3.6V)) |
| 24 | SPIHD | I/O | Multiplexed I/O & Peripheral Pin SPIHD (SPI) |
| 25 | SPICLK | I/O | Multiplexed I/O & Peripheral Pin SPICLK (SPI) |
| 26 | SPID | I/O | Multiplexed I/O & Peripheral Pin SPID (SPI) |
| 27 | GPIO15 | I/O | Multiplexed I/O & Peripheral Pin GPIO15 (General) |
| 28 | VDDPST2 | Power | Power Supply Input (VDDPST2 — 3.3V VDD3P3 (3.0V ~ 3.6V)) |
| 29 | U0TXD | I/O | Multiplexed I/O & Peripheral Pin U0TXD (UART) |
| 30 | U0RXD | I/O | Multiplexed I/O & Peripheral Pin U0RXD (UART) |
| 31 | SDIO_CMD | I/O | Multiplexed I/O & Peripheral Pin SDIO_CMD (General) |
| 32 | SDIO_CLK | I/O | Multiplexed I/O & Peripheral Pin SDIO_CLK (General) |
| 33 | SDIO_DATA0 | I/O | Multiplexed I/O & Peripheral Pin SDIO_DATA0 (General) |
| 34 | SDIO_DATA1 | I/O | Multiplexed I/O & Peripheral Pin SDIO_DATA1 (General) |
| 35 | SDIO_DATA2 | I/O | Multiplexed I/O & Peripheral Pin SDIO_DATA2 (General) |
| 36 | SDIO_DATA3 | I/O | Multiplexed I/O & Peripheral Pin SDIO_DATA3 (General) |
| 37 | VDDA1 | Power | Power Supply Input (VDDA1 — 3.3V VDD3P3 (3.0V ~ 3.6V)) |
| 38 | XTAL_N | I/O | Multiplexed I/O & Peripheral Pin XTAL_N (RTC/CLK) |
| 39 | XTAL_P | I/O | Multiplexed I/O & Peripheral Pin XTAL_P (RTC/CLK) |
| 40 | VDDA2 | Power | Power Supply Input (VDDA2 — 3.3V VDD3P3 (3.0V ~ 3.6V)) |
| 41 | EP | GND | Exposed Thermal & Ground Pad (EP) |
PIN 1 ANT
I/OMultiplexed I/O & Peripheral Pin ANT (General)
Design note: Signal terminal ANT (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (41 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN-40-EP(5x5) · 5.00×5.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (41 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for ESP32-C6
P13 · p13_fig01EXACT PACKAGE
P71 · p71_fig01EXACT PACKAGE
P1 · p01_fig01336×313px
P2 · p02_fig011739×1869px
P13 · p13_fig02871×282px
P13 · p13_fig01P13
P2 · p02_fig021271×826px
Technical Specifications & Part Details (ESP32-C6)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:ESP32-C6 (QFN-40-EP(5x5)) is a 40-pin wireless wi-fi / bluetooth le soc module featuring a 5.00 × 5.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Wi-Fi, Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_TX(peak) ≈ 310 mA @ 3.3V | Deep-Sleep ≈ 10 µA | I_GPIO(max) = 40 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-40-EP(5x5))
Pin Count & Lead PitchN / e
40 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (MTDI, MTDO): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol41 auto-grouped pins
IPC-7351B Land Pattern41 pads · Pitch 0.40mm
IPC-7525 60% Solder PasteEPAD 3.30×3.30mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — ESP32-C6 (2)
QFN-40-EP(5x5) · 41P
Mechanical Dimensions & Land Pattern (QFN-40-EP(5x5))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
41P / 41Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| C1, C2 BOM | 22µF (or 10µF) X5R + 100nF X7R 0805 + 0402 | 3V3 supply decoupling for ~500mA Wi-Fi TX bursts — place closest to 3V3 pin; supply must deliver >= 600mA. |
| R_en + C_en BOM | R = 10kΩ to 3V3 + C = 1µF to GND 0402 / 0603 | Power-On Reset RC delay at EN (CHIP_PU) — 1µF capacitor at EN is REQUIRED for reliable cold boot. |
| R_boot + SW1 BOM | 10kΩ Pull-up + BOOT button 0402 + SMD | Firmware boot-mode strap (IO0 on ESP32/S2/S3, IO9 on ESP32-C3) — on C3 pull IO8 high via 10kΩ for UART/USB download. |
| D_esd BOM | USBLC6-2SC6 / LESD5D5.0CT1G SOT-23-6 / SOD-523 | ESD surge protection on USB D+/D- — place right next to USB Type-C connector before IO18/IO19/IO20. |
| ESP32-S3-MINI-1-N8 / 1U-N4R2 Espressif | 100% Drop-in | Same 15.4×15.4mm 65-pad footprint as ESP32-S2-MINI-2 — verify USB GPIO 19/20 pin mapping. |
Technical Frequently Asked Questions (FAQ) — ESP32-C6 (QFN-40-EP(5x5))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of ESP32-C6 (QFN-40-EP(5x5))?
Manufactured by ESPRESSIF, the ESP32-C6 is housed in a QFN-40-EP(5x5) package with 41 pins and a 0.40 mm lead pitch. Key pins include: 1 (ANT: Multiplexed I/O & Peripheral Pin ANT (General)), 2 (VDDA3P3: Power Supply Input (VDDA3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 3 (VDDA3P3: Power Supply Input (VDDA3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 4 (CHIP_PU: System Enable & Hardware Reset (CHIP_PU)), 5 (VDDPST1: Power Supply Input (VDDPST1 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 6 (XTAL_32K_P: Multiplexed I/O & Peripheral Pin XTAL_32K_P (RTC/CLK)).
What are the IPC-7351B PCB Footprint dimensions for ESP32-C6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP32-C6 (QFN-40-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.40 mm, and 41 copper pads plus a central exposed thermal pad (EPAD) of 3.30 × 3.30 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP32-C6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP32-C6 (ESPRESSIF, QFN-40-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (41 pins) & ESP32-C6 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | ANT | RF_50Ohm | Signal terminal ANT (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General. |
| 2 | VDDA3P3 | Power_In | Primary positive power supply input (VDDA3P3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V). |
| 3 | VDDA3P3 | Power_In | Primary positive power supply input (VDDA3P3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V). |
| 4 | CHIP_PU | Digital_IO | Chip enable and power-on reset control input (CHIP_PU): High enables the SoC; Low powers down the chip into reset. |
| 5 | VDDPST1 | Power_In | Primary positive power supply input (VDDPST1) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V). |
| 6 | XTAL_32K_P | Digital_IO | Signal terminal XTAL_32K_P (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_32K_P. Supported peripheral buses: RTC/CLK. |
| 7 | XTAL_32K_N | Digital_IO | Signal terminal XTAL_32K_N (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_32K_N. Supported peripheral buses: RTC/CLK. |
| 8 | GPIO2 | Digital_IO | Signal terminal GPIO2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General. |
| 9 | GPIO3 | Digital_IO | Signal terminal GPIO3 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General. |
| 10 | MTMS | Digital_IO | Signal terminal MTMS (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTMS. Supported peripheral buses: SWD/JTAG. |
| 11 | MTDI | Digital_IO | Signal terminal MTDI (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTDI. Supported peripheral buses: SWD/JTAG. |
| 12 | MTCK | Digital_IO | Signal terminal MTCK (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTCK. Supported peripheral buses: SWD/JTAG. |
| 13 | MTDO | Digital_IO | Signal terminal MTDO (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTDO. Supported peripheral buses: SWD/JTAG. |
| 14 | GPIO8 | Digital_IO | Signal terminal GPIO8 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO8. Supported peripheral buses: General. |
| 15 | GPIO9 | Digital_IO | Signal terminal GPIO9 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO9. Supported peripheral buses: General. |
| 16 | GPIO10 | Digital_IO | Signal terminal GPIO10 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO10. Supported peripheral buses: General. |
| 17 | GPIO11 | Digital_IO | Signal terminal GPIO11 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO11. Supported peripheral buses: General. |
| 18 | GPIO12 | Digital_IO | Signal terminal GPIO12 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO12. Supported peripheral buses: General. |
| 19 | GPIO13 | Digital_IO | Signal terminal GPIO13 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO13. Supported peripheral buses: General. |
| 20 | SPICS0 | Digital_IO | Signal terminal SPICS0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPICS0. Supported peripheral buses: SPI. |
| 21 | SPIQ | Digital_IO | Signal terminal SPIQ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIQ. Supported peripheral buses: SPI. |
| 22 | SPIWP | Digital_IO | Signal terminal SPIWP (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIWP. Supported peripheral buses: SPI. |
| 23 | VDD_SPI | Power_Out | Regulated power output rail (VDD_SPI) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V). |
| 24 | SPIHD | Digital_IO | Signal terminal SPIHD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIHD. Supported peripheral buses: SPI. |
| 25 | SPICLK | Digital_IO | Signal terminal SPICLK (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPICLK. Supported peripheral buses: SPI. |
| 26 | SPID | Digital_IO | Signal terminal SPID (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPID. Supported peripheral buses: SPI. |
| 27 | GPIO15 | Digital_IO | Signal terminal GPIO15 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO15. Supported peripheral buses: General. |
| 28 | VDDPST2 | Power_In | Primary positive power supply input (VDDPST2) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V). |
| 29 | U0TXD | Digital_IO | Signal terminal U0TXD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0TXD. Supported peripheral buses: UART. |
| 30 | U0RXD | Digital_IO | Signal terminal U0RXD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0RXD. Supported peripheral buses: UART. |
| 31 | SDIO_CMD | Digital_IO | Signal terminal SDIO_CMD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SDIO_CMD. Supported peripheral buses: General. |
| 32 | SDIO_CLK | Digital_IO | Signal terminal SDIO_CLK (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SDIO_CLK. Supported peripheral buses: General. |
| 33 | SDIO_DATA0 | Digital_IO | Signal terminal SDIO_DATA0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SDIO_DATA0. Supported peripheral buses: General. |
| 34 | SDIO_DATA1 | Digital_IO | Signal terminal SDIO_DATA1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SDIO_DATA1. Supported peripheral buses: General. |
| 35 | SDIO_DATA2 | Digital_IO | Signal terminal SDIO_DATA2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SDIO_DATA2. Supported peripheral buses: General. |
| 36 | SDIO_DATA3 | Digital_IO | Signal terminal SDIO_DATA3 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SDIO_DATA3. Supported peripheral buses: General. |
| 37 | VDDA1 | Power_In | Primary positive power supply input (VDDA1) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V). |
| 38 | XTAL_N | Digital_IO | Signal terminal XTAL_N (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_N. Supported peripheral buses: RTC/CLK. |
| 39 | XTAL_P | Digital_IO | Signal terminal XTAL_P (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_P. Supported peripheral buses: RTC/CLK. |
| 40 | VDDA2 | Power_In | Primary positive power supply input (VDDA2) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V). |
| 41 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |