SOP-8 · 8P
Synchronized Pinout (Symbol / 2D / 3D) (8/8)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | GND | GND | Ground Reference Pin (GND) |
| 2 | TXD | I/O | Multiplexed I/O & Peripheral Pin TXD (UART) |
| 3 | VIO | I/O | Multiplexed I/O & Peripheral Pin VIO (General) |
| 4 | RXD | I/O | Multiplexed I/O & Peripheral Pin RXD (UART) |
| 5 | UD+ | I/O | Multiplexed I/O & Peripheral Pin UD+ (USB) |
| 6 | UD- | I/O | Multiplexed I/O & Peripheral Pin UD- (USB) |
| 7 | VDD5 | Power | Power Supply Input (VDD5 — 3.3V to 5V) |
| 8 | V3 | Power | Regulated Power Output (V3 — 3.3V to 5V) |
PIN 1 GND
GNDGround Reference Pin (GND)
Design note: 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (8 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SOP-8 · 3.90×4.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (8 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH9101
P10 · p10_fig01EXACT PACKAGE
P1 · p01_fig011463×442px
P2 · p02_fig011654×1399px
P2 · p02_fig021736×555px
P2 · p02_fig01P2
P10 · p10_fig021452×974px
P10 · p10_fig02P10
P11 · p11_fig01899×663px
P11 · p11_fig02849×382px
Technical Specifications & Part Details (CH9101N)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH9101N (SOP-8) is a 8-pin standard electronic & interconnect component featuring a 4.90 × 3.90 × 1.75 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 3.3V to 5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.3V to 5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.90 × 3.90 × 1.75 mm (A1=0.15 mm)
Package family: SOP (SOP-8)
Pin Count & Lead PitchN / e
8 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol8 auto-grouped pins
IPC-7351B Land Pattern8 pads · Pitch 1.27mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH9101 (4)
QSOP-16-150mil · 16P
QFN-16(4x4) · 17P
SSOP-28-209mil · 28P
Mechanical Dimensions & Land Pattern (SOP-8)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
4.90 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.75mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.55 mm
Pins / Total PadsTopology
8P / 8Pad (DUAL_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SOP-8 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH9101N (SOP-8)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH9101N (SOP-8)?
Manufactured by WCH, the CH9101N is housed in a SOP-8 package with 8 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 3.3V to 5V. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (TXD: Multiplexed I/O & Peripheral Pin TXD (UART)), 3 (VIO: Multiplexed I/O & Peripheral Pin VIO (General)), 4 (RXD: Multiplexed I/O & Peripheral Pin RXD (UART)), 5 (UD+: Multiplexed I/O & Peripheral Pin UD+ (USB)), 6 (UD-: Multiplexed I/O & Peripheral Pin UD- (USB)).
What are the IPC-7351B PCB Footprint dimensions for CH9101N?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9101N (SOP-8) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.27 mm, and 8 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9101N?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9101N (WCH, SOP-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (8 pins) & CH9101 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 2 | TXD | Digital_IO | Signal terminal TXD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART. |
| 3 | VIO | Digital_IO | Signal terminal VIO (I/O, 3.3V to 5V domain). Multiplexed alternate functions: VIO. Supported peripheral buses: General. |
| 4 | RXD | Digital_IO | Signal terminal RXD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART. |
| 5 | UD+ | Digital_IO | Signal terminal UD+ (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB. |
| 6 | UD- | Digital_IO | Signal terminal UD- (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB. |
| 7 | VDD5 | Power_In | Primary positive power supply input (VDD5) operating in the 3.3V to 5V domain (Max rating: 5.0V). |
| 8 | V3 | Power_Out | Regulated power output rail (V3) operating in the 3.3V to 5V domain (Max rating: 5.0V). |