MIC2230-AAYML-TR (TDFN-12-EP(3x3)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of MIC2230-AAYML-TR (TDFN-12-EP(3x3))?

Manufactured by MICROCHIP, the MIC2230-AAYML-TR is housed in a TDFN-12-EP(3x3) package with 13 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.5V to 5.5V. Key pins include: 1 (FB2: Multiplexed I/O & Peripheral Pin FB2 (General)), 2 (EN2: Multiplexed I/O & Peripheral Pin EN2 (General)), 3 (AVIN: Power Supply Input (AVIN — 2.5V to 5.5V)), 4 (SW2: Multiplexed I/O & Peripheral Pin SW2 (General)), 5 (AGND: Ground Reference Pin (AGND)), 6 (PGND: Ground Reference Pin (PGND)).

Q: What are the IPC-7351B PCB Footprint dimensions for MIC2230-AAYML-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC2230-AAYML-TR (TDFN-12-EP(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 13 copper pads plus a central exposed thermal pad (EPAD) of 2.50 × 1.60 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC2230-AAYML-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC2230-AAYML-TR (MICROCHIP, TDFN-12-EP(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 3.00mm × 3.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (13/13)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	FB2	I/O	Multiplexed I/O & Peripheral Pin FB2 (General)
2	EN2	I/O	Multiplexed I/O & Peripheral Pin EN2 (General)
3	AVIN	Power	Power Supply Input (AVIN — 2.5V to 5.5V)
4	SW2	I/O	Multiplexed I/O & Peripheral Pin SW2 (General)
5	AGND	GND	Ground Reference Pin (AGND)
6	PGND	GND	Ground Reference Pin (PGND)
7	/FPWM	I/O	Multiplexed I/O & Peripheral Pin /FPWM (General)
8	SW1	I/O	Multiplexed I/O & Peripheral Pin SW1 (General)
9	VIN	Power	Power Supply Input (VIN — 2.5V to 5.5V)
10	PGOOD	I/O	Multiplexed I/O & Peripheral Pin PGOOD (General)
11	EN1	I/O	Multiplexed I/O & Peripheral Pin EN1 (General)
12	FB1	I/O	Multiplexed I/O & Peripheral Pin FB1 (General)
13	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 FB2

I/O

Multiplexed I/O & Peripheral Pin FB2 (General)

Design note: Feedback 2: For adjustable voltage options connect the exter- nalresistordividernetworktoFB2tosettheoutputvoltageof regulator2 Nominalvalueis08V . . .

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

MIC2230-AAYML-TR (TDFN-12-EP(3x3)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

MIC2230-AAYML-TR (TDFN-12-EP(3x3)) - 2. Standard Pinout (Top View)

True package pinout (13 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

MIC2230-AAYML-TR (TDFN-12-EP(3x3)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

MIC2230-AAYML-TR (TDFN-12-EP(3x3)) - 4. Package Dimensions (D×E×A)

TDFN-12-EP(3x3) · 3.00×3.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

MIC2230-AAYML-TR (TDFN-12-EP(3x3)) - 5. Recommended Land Pattern

IPC-7351B Footprint (13 Pads)Expand ›

6. Application SchematicSCHEMATIC

MIC2230-AAYML-TR (TDFN-12-EP(3x3)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)

Showing 1–9 of 9 uncropped original figures for MIC2230

P1 · p01_fig02EXACT PACKAGE

MIC2230-AAYML-TR (TDFN-12-EP(3x3)) —  2017 Microchip Technology Inc. DS20005748A-page 1 | Applications | • MPU & ASIC Power • PDAs • Digital Cameras • PC Cards • Wireless and DSL Modems | The MIC2230 is available in a space-saving 3 mm × 3 mm TDFN-12L package with a junction

 2017 Microchip Technology Inc. DS20005748A-page 1 | Applications | • MPU & ASIC Power • PDAs • Digital Cameras • PC Cards • Wireless and DSL Modems | The MIC2230 is available in a space-saving 3 mm × 3 mm TDFN-12L package with a junction

P1 · p01_fig01377×200px

Dual Synchronous 800 mA/800 mA Step-Down DC/DC Regulator

P1 · p01_fig02P1

Datasheet Page 1 (p01_fig02)

P2 · p02_fig011777×717px

Typical Application Circuit

P2 · p02_fig021775×1134px

MIC2230-AAYML-TR (TDFN-12-EP(3x3)) — Functional Block Diagram | Compensation | Trickle Mode | Logic | Anti Shoot-through Logic | HSD | LSD | Anti Shoot-through | Logic | HSD | LSD | ENABLE | LOGIC | VIN | EN1 | SW1 | PGOOD | FB1 | PGND AGND | FB2 | /FPWM | SW2 | EN2 | AVIN | I

Functional Block Diagram | Compensation | Trickle Mode | Logic | Anti Shoot-through Logic | HSD | LSD | Anti Shoot-through | Logic | HSD | LSD | ENABLE | LOGIC | VIN | EN1 | SW1 | PGOOD | FB1 | PGND AGND | FB2 | /FPWM | SW2 | EN2 | AVIN | I

P2 · p02_fig01P2

Datasheet Page 2 (p02_fig01)

P11 · p11_fig01866×608px

FIGURE 4-1: Power Good Circuit. 4.7 FB1/FB2

P13 · p13_fig01780×489px

The MIC2230 was designed for use with a 2.2 μH inductor.

P18 · p18_fig011567×1558px

MIC2230

Technical Specifications & Part Details (MIC2230-AAYML-TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:MIC2230-AAYML-TR (TDFN-12-EP(3x3)) is a 12-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.5V to 5.5V supply operation across 40°C to +125°C with integrated PWM interfaces.

Operating Supply VoltageV_CC / V_DD

2.5V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

40°C to +125°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

2.5 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

28 μA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

3.00 × 3.00 × 0.85 mm (A1=0.03 mm)

Package family: DFN (TDFN-12-EP(3x3))

Pin Count & Lead PitchN / e

12 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

PWM

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol13 auto-grouped pins

IPC-7351B Land Pattern13 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteEPAD 2.50×1.60mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TDFN-12-EP(3x3))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

3.00 × 3.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.85mm · e=0.50mm

Pad Size (W × L)Level B

0.25 × 0.60 mm

Pins / Total PadsTopology

13P / 13Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit TDFN-12-EP(3x3)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MIC2230-AAYML-TR (TDFN-12-EP(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MIC2230-AAYML-TR (TDFN-12-EP(3x3))?

Manufactured by MICROCHIP, the MIC2230-AAYML-TR is housed in a TDFN-12-EP(3x3) package with 13 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.5V to 5.5V. Key pins include: 1 (FB2: Multiplexed I/O & Peripheral Pin FB2 (General)), 2 (EN2: Multiplexed I/O & Peripheral Pin EN2 (General)), 3 (AVIN: Power Supply Input (AVIN — 2.5V to 5.5V)), 4 (SW2: Multiplexed I/O & Peripheral Pin SW2 (General)), 5 (AGND: Ground Reference Pin (AGND)), 6 (PGND: Ground Reference Pin (PGND)).

What are the IPC-7351B PCB Footprint dimensions for MIC2230-AAYML-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC2230-AAYML-TR (TDFN-12-EP(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 13 copper pads plus a central exposed thermal pad (EPAD) of 2.50 × 1.60 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC2230-AAYML-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC2230-AAYML-TR (MICROCHIP, TDFN-12-EP(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (13 pins) & MIC2230 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	FB2	Digital_IO	Signal terminal FB2 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: FB2. Supported peripheral buses: General.
2	EN2	Digital_IO	Signal terminal EN2 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: EN2. Supported peripheral buses: General.
3	AVIN	Power_In	Primary positive power supply input (AVIN) operating in the 2.5V to 5.5V domain (Max rating: 5.5V).
4	SW2	Digital_IO	Signal terminal SW2 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: SW2. Supported peripheral buses: General.
5	AGND	GND	0V electrical ground return terminal (AGND) for internal core logic, I/O drivers, and analog sub-blocks.
6	PGND	GND	0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks.
7	/FPWM	Digital_IO	Signal terminal /FPWM (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: /FPWM. Supported peripheral buses: General.
8	SW1	Digital_IO	Signal terminal SW1 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: SW1. Supported peripheral buses: General.
9	VIN	Power_In	Primary positive power supply input (VIN) operating in the 2.5V to 5.5V domain (Max rating: 5.5V).
10	PGOOD	Digital_IO	Signal terminal PGOOD (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: PGOOD. Supported peripheral buses: General.
11	EN1	Digital_IO	Signal terminal EN1 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: EN1. Supported peripheral buses: General.
12	FB1	Digital_IO	Signal terminal FB1 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: FB1. Supported peripheral buses: General.
13	EP	GND	Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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