KSZ9031RNXCA-TR (QFN-48-EP(7x7)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of KSZ9031RNXCA-TR (QFN-48-EP(7x7))?

Manufactured by MICROCHIP, the KSZ9031RNXCA-TR is housed in a QFN-48-EP(7x7) package with 49 pins and a 0.50 mm lead pitch. Key pins include: 1 (AVDDH: Power Supply Input (AVDDH — 3.3V / 5.0V Standard Logic)), 2 (TXRXP_A: Multiplexed I/O & Peripheral Pin TXRXP_A (General)), 3 (TXRXM_A: Multiplexed I/O & Peripheral Pin TXRXM_A (General)), 4 (AVDDL: Power Supply Input (AVDDL — 3.3V / 5.0V Standard Logic)), 5 (TXRXP_B: Multiplexed I/O & Peripheral Pin TXRXP_B (General)), 6 (TXRXM_B: Multiplexed I/O & Peripheral Pin TXRXM_B (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for KSZ9031RNXCA-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), KSZ9031RNXCA-TR (QFN-48-EP(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.10 × 5.10 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for KSZ9031RNXCA-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for KSZ9031RNXCA-TR (MICROCHIP, QFN-48-EP(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	AVDDH	Power	Power Supply Input (AVDDH — 3.3V / 5.0V Standard Logic)
2	TXRXP_A	I/O	Multiplexed I/O & Peripheral Pin TXRXP_A (General)
3	TXRXM_A	I/O	Multiplexed I/O & Peripheral Pin TXRXM_A (General)
4	AVDDL	Power	Power Supply Input (AVDDL — 3.3V / 5.0V Standard Logic)
5	TXRXP_B	I/O	Multiplexed I/O & Peripheral Pin TXRXP_B (General)
6	TXRXM_B	I/O	Multiplexed I/O & Peripheral Pin TXRXM_B (General)
7	TXRXP_C	I/O	Multiplexed I/O & Peripheral Pin TXRXP_C (General)
8	TXRXM_C	I/O	Multiplexed I/O & Peripheral Pin TXRXM_C (General)
9	AVDDL	Power	Power Supply Input (AVDDL — 3.3V / 5.0V Standard Logic)
10	TXRXP_D	I/O	Multiplexed I/O & Peripheral Pin TXRXP_D (General)
11	TXRXM_D	I/O	Multiplexed I/O & Peripheral Pin TXRXM_D (General)
12	AVDDH	Power	Power Supply Input (AVDDH — 3.3V / 5.0V Standard Logic)
13	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
14	DVDDL	Power	Power Supply Input (DVDDL — 3.3V / 5.0V Standard Logic)
15	LED2/ PHYAD1	I/O	Multiplexed I/O & Peripheral Pin LED2/ PHYAD1 (General)
16	DVDDH	Power	Power Supply Input (DVDDH — 3.3V / 5.0V Standard Logic)
17	LED1/ PHYAD0/ PME_N1	I/O	Multiplexed I/O & Peripheral Pin LED1/ PHYAD0/ PME_N1 (General)
18	DVDDL	Power	Power Supply Input (DVDDL — 3.3V / 5.0V Standard Logic)
19	TXD0	I/O	Multiplexed I/O & Peripheral Pin TXD0 (UART)
20	TXD1	I/O	Multiplexed I/O & Peripheral Pin TXD1 (UART)
21	TXD2	I/O	Multiplexed I/O & Peripheral Pin TXD2 (UART)
22	TXD3	I/O	Multiplexed I/O & Peripheral Pin TXD3 (UART)
23	DVDDL	Power	Power Supply Input (DVDDL — 3.3V / 5.0V Standard Logic)
24	GTX_CLK	I/O	Multiplexed I/O & Peripheral Pin GTX_CLK (General)
25	TX_EN	I/O	Multiplexed I/O & Peripheral Pin TX_EN (General)
26	DVDDL	Power	Power Supply Input (DVDDL — 3.3V / 5.0V Standard Logic)
27	RXD3/ MODE3	I/O	Multiplexed I/O & Peripheral Pin RXD3/ MODE3 (UART)
28	RXD2/ MODE2	I/O	Multiplexed I/O & Peripheral Pin RXD2/ MODE2 (UART)
29	VSS	GND	Ground Reference Pin (VSS)
30	DVDDL	Power	Power Supply Input (DVDDL — 3.3V / 5.0V Standard Logic)
31	RXD1/ MODE1	I/O	Multiplexed I/O & Peripheral Pin RXD1/ MODE1 (UART)
32	RXD0/ MODE0	I/O	Multiplexed I/O & Peripheral Pin RXD0/ MODE0 (UART)
33	CLK125_EN	I/O	Multiplexed I/O & Peripheral Pin CLK125_EN (General)
34	DVDDH	Power	Power Supply Input (DVDDH — 3.3V / 5.0V Standard Logic)
35	RX CLK/_ PHYAD2	I/O	Multiplexed I/O & Peripheral Pin RX CLK/_ PHYAD2 (General)
36	MDC	I/O	Multiplexed I/O & Peripheral Pin MDC (General)
37	MDIO	I/O	Multiplexed I/O & Peripheral Pin MDIO (General)
38	INT N/_ PME_N2	I/O	Multiplexed I/O & Peripheral Pin INT N/_ PME_N2 (General)
39	DVDDL	Power	Power Supply Input (DVDDL — 3.3V / 5.0V Standard Logic)
40	DVDDH	Power	Power Supply Input (DVDDH — 3.3V / 5.0V Standard Logic)
41	LED_MODE	I/O	Multiplexed I/O & Peripheral Pin LED_MODE (General)
42	RESET_N	I	System Enable & Hardware Reset (RESET_N)
43	LDO_O	I/O	Multiplexed I/O & Peripheral Pin LDO_O (General)
44	AVDDL_PLL	Power	Power Supply Input (AVDDL_PLL — 3.3V / 5.0V Standard Logic)
45	XO	I/O	Multiplexed I/O & Peripheral Pin XO (RTC/CLK)
46	XI	I/O	Multiplexed I/O & Peripheral Pin XI (RTC/CLK)
47	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
48	ISET	I/O	Multiplexed I/O & Peripheral Pin ISET (General)
49	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 AVDDH

Power

Power Supply Input (AVDDH — 3.3V / 5.0V Standard Logic)

Design note: 3 .3V/2 .5V (commercial temp only) analog VDD

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

KSZ9031RNXCA-TR (QFN-48-EP(7x7)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

KSZ9031RNXCA-TR (QFN-48-EP(7x7)) - 2. Standard Pinout (Top View)

True package pinout (49 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

KSZ9031RNXCA-TR (QFN-48-EP(7x7)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

KSZ9031RNXCA-TR (QFN-48-EP(7x7)) - 4. Package Dimensions (D×E×A)

QFN-48-EP(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

KSZ9031RNXCA-TR (QFN-48-EP(7x7)) - 5. Recommended Land Pattern

IPC-7351B Footprint (49 Pads)Expand ›

6. Application SchematicSCHEMATIC

KSZ9031RNXCA-TR (QFN-48-EP(7x7)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)

Showing 1–12 of 14 uncropped original figures for KSZ9031

P1 · p01_fig01376×200px

Gigabit Ethernet Transceiver with RGMII

P5 · p05_fig011428×1490px

FIGURE 2-1: 48-QFN PIN ASSIGNMENT (TOP VIEW)

P5 · p05_fig01P5

Datasheet Page 5 (p05_fig01)

P65 · p65_fig011127×962px

FIGURE 9-1: REFERENCE CIRCUITS FOR LED STRAPPING PINS

P65 · p65_fig01P65

Datasheet Page 65 (p65_fig01)

P66 · p66_fig011576×498px

FIGURE 10-1: 25 MHZ CRYSTAL/OSCILLATOR REFERENCE CLOCK CONNECTION

P67 · p67_fig011380×979px

FIGURE 12-1: TYPICAL GIGABIT MAGNETIC INTERFACE CIRCUIT

P67 · p67_fig02345×703px

FIGURE 12-1: TYPICAL GIGABIT MAGNETIC INTERFACE CIRCUIT

P67 · p67_fig031779×347px

KSZ9031RNXCA-TR (QFN-48-EP(7x7)) — DS00002117F-page 67  2016-2017 Microchip Technology Inc. | Table 12-2 is a list of compatible single-port magnetics with separated transformer center tap pins on the G-PHY chip side that can be used with the KSZ9031RNX. | TABLE 12-2: COMPA

DS00002117F-page 67  2016-2017 Microchip Technology Inc. | Table 12-2 is a list of compatible single-port magnetics with separated transformer center tap pins on the G-PHY chip side that can be used with the KSZ9031RNX. | TABLE 12-2: COMPA

P69 · p69_fig011579×1570px

FIGURE 13-1: 48-LEAD QFN 7 MM X 7 MM PACKAGE WITH 3.5 MM X 3.5 MM EXPOSED PAD AREA

P70 · p70_fig011578×1528px

FIGURE 13-2: 48-LEAD QFN 7 MM X 7 MM PACKAGE WITH 5.1 MM X 5.1 MM EXPOSED PAD AREA

P71 · p71_fig011580×1701px

FIGURE 13-3: 48-LEAD QFN 7 MM X 7 MM PACKAGE WITH 5.1 MM X 5.1 MM EXPOSED PAD AREA RECOMMENDED LAND PATTERN

Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (KSZ9031RNXCA-TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:KSZ9031RNXCA-TR (QFN-48-EP(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 55°C to +150°C with integrated RTC/CLK, UART interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

55°C to +150°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

125 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

7.00 × 7.00 × 0.85 mm (A1=0.03 mm)

Package family: QFN (QFN-48-EP(7x7))

Pin Count & Lead PitchN / e

48 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

RTC/CLK, UART

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Boot Strapping Pin Alert (LED2/ PHYAD1, LED1/ PHYAD0/ PME_N1): Do not force conflicting external pull-ups/pull-downs during POR reset.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol49 auto-grouped pins

IPC-7351B Land Pattern49 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteEPAD 5.10×5.10mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-48-EP(7x7))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

7.00 × 7.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.85mm · e=0.50mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-48-EP(7x7)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — KSZ9031RNXCA-TR (QFN-48-EP(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of KSZ9031RNXCA-TR (QFN-48-EP(7x7))?

Manufactured by MICROCHIP, the KSZ9031RNXCA-TR is housed in a QFN-48-EP(7x7) package with 49 pins and a 0.50 mm lead pitch. Key pins include: 1 (AVDDH: Power Supply Input (AVDDH — 3.3V / 5.0V Standard Logic)), 2 (TXRXP_A: Multiplexed I/O & Peripheral Pin TXRXP_A (General)), 3 (TXRXM_A: Multiplexed I/O & Peripheral Pin TXRXM_A (General)), 4 (AVDDL: Power Supply Input (AVDDL — 3.3V / 5.0V Standard Logic)), 5 (TXRXP_B: Multiplexed I/O & Peripheral Pin TXRXP_B (General)), 6 (TXRXM_B: Multiplexed I/O & Peripheral Pin TXRXM_B (General)).

What are the IPC-7351B PCB Footprint dimensions for KSZ9031RNXCA-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), KSZ9031RNXCA-TR (QFN-48-EP(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.10 × 5.10 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for KSZ9031RNXCA-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for KSZ9031RNXCA-TR (MICROCHIP, QFN-48-EP(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & KSZ9031 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	AVDDH	Power_In	Primary positive power supply input (AVDDH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2	TXRXP_A	Digital_IO	Signal terminal TXRXP_A (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXP_A. Supported peripheral buses: General.
3	TXRXM_A	Digital_IO	Signal terminal TXRXM_A (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXM_A. Supported peripheral buses: General.
4	AVDDL	Power_In	Primary positive power supply input (AVDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
5	TXRXP_B	Digital_IO	Signal terminal TXRXP_B (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXP_B. Supported peripheral buses: General.
6	TXRXM_B	Digital_IO	Signal terminal TXRXM_B (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXM_B. Supported peripheral buses: General.
7	TXRXP_C	Digital_IO	Signal terminal TXRXP_C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXP_C. Supported peripheral buses: General.
8	TXRXM_C	Digital_IO	Signal terminal TXRXM_C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXM_C. Supported peripheral buses: General.
9	AVDDL	Power_In	Primary positive power supply input (AVDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
10	TXRXP_D	Digital_IO	Signal terminal TXRXP_D (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXP_D. Supported peripheral buses: General.
11	TXRXM_D	Digital_IO	Signal terminal TXRXM_D (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXRXM_D. Supported peripheral buses: General.
12	AVDDH	Power_In	Primary positive power supply input (AVDDH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
13	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14	DVDDL	Power_In	Primary positive power supply input (DVDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
15	LED2/ PHYAD1	Digital_IO	Signal terminal LED2/ PHYAD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED2/ PHYAD1. Supported peripheral buses: General.
16	DVDDH	Power_In	Primary positive power supply input (DVDDH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
17	LED1/ PHYAD0/ PME_N1	Open_Drain	Signal terminal LED1/ PHYAD0/ PME_N1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED1/ PHYAD0/ PME_N1. Supported peripheral buses: General.
18	DVDDL	Power_In	Primary positive power supply input (DVDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
19	TXD0	Digital_IO	Signal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
20	TXD1	Digital_IO	Signal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
21	TXD2	Digital_IO	Signal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART.
22	TXD3	Digital_IO	Signal terminal TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART.
23	DVDDL	Power_In	Primary positive power supply input (DVDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
24	GTX_CLK	Digital_IO	Signal terminal GTX_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GTX_CLK. Supported peripheral buses: General.
25	TX_EN	Digital_IO	Signal terminal TX_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TX_EN. Supported peripheral buses: General.
26	DVDDL	Power_In	Primary positive power supply input (DVDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
27	RXD3/ MODE3	Digital_IO	Signal terminal RXD3/ MODE3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3/ MODE3. Supported peripheral buses: UART.
28	RXD2/ MODE2	Digital_IO	Signal terminal RXD2/ MODE2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2/ MODE2. Supported peripheral buses: UART.
29	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
30	DVDDL	Power_In	Primary positive power supply input (DVDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
31	RXD1/ MODE1	Digital_IO	Signal terminal RXD1/ MODE1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1/ MODE1. Supported peripheral buses: UART.
32	RXD0/ MODE0	Digital_IO	Signal terminal RXD0/ MODE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0/ MODE0. Supported peripheral buses: UART.
33	CLK125_EN	Digital_IO	Signal terminal CLK125_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLK125_EN. Supported peripheral buses: General.
34	DVDDH	Power_In	Primary positive power supply input (DVDDH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
35	RX CLK/_ PHYAD2	Digital_IO	Signal terminal RX CLK/_ PHYAD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RX CLK/_ PHYAD2. Supported peripheral buses: General.
36	MDC	Digital_IO	Signal terminal MDC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDC. Supported peripheral buses: General.
37	MDIO	Digital_IO	Signal terminal MDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIO. Supported peripheral buses: General.
38	INT N/_ PME_N2	Open_Drain	Signal terminal INT N/_ PME_N2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT N/_ PME_N2. Supported peripheral buses: General.
39	DVDDL	Power_In	Primary positive power supply input (DVDDL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
40	DVDDH	Power_In	Primary positive power supply input (DVDDH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
41	LED_MODE	Digital_IO	Signal terminal LED_MODE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_MODE. Supported peripheral buses: General.
42	RESET_N	Digital_IO	Active-low hardware reset terminal (RESET_N): pulling this pin Low resets the processor core and peripherals.
43	LDO_O	Digital_IO	Signal terminal LDO_O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LDO_O. Supported peripheral buses: General.
44	AVDDL_PLL	Power_In	Primary positive power supply input (AVDDL_PLL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
45	XO	Digital_IO	Signal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
46	XI	Digital_IO	Signal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
47	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
48	ISET	Digital_IO	Signal terminal ISET (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ISET. Supported peripheral buses: General.
49	EP	GND	Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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