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CH32F203RCT6 (LQFP-64M(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32F203RCT6

WCHID: C5137038LQFP-64M(10x10) · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32F203RCT6 (LQFP-64M(10x10))1VBAT2PC13 - TAMPE3PC14 - OSC324PC15 - OSC325OSC_IN6OSC_OUT7NRST8PC09PC110PC211PC312VSSA13VDDA14PA0 WKUP -15PA116PA217PA318V_SS419V_DD420PA421PA522PA623PA724PC425PC526PB027PB128PB229PB1030PB1131VSS1_32V_IO164V_IO363VSS3_62PB961PB860BOOT059PB758PB657PB556PB455PB354PD253PC1252PC1151PC1050PA1549PA1448VDD2_47VSS2_46PA1345PA1244PA1143PA1042PA941PA840PC939PC838PC737PC636PB1535PB1434PB1333PB12Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=10.00mm · Pitch e=0.50mmD=10.00mm-9-7-5-3-11357997531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
2PC13 - TAMPER RTC(2) -I/OMultiplexed I/O & Peripheral Pin PC13 - TAMPER RTC(2) - (RTC/CLK)
3PC14 - OSC32 IN(2)_I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32 IN(2)_ (RTC/CLK)
4PC15 - OSC32 OUT(2)_I/OMultiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(2)_ (RTC/CLK)
5OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
6OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8PC0I/OMultiplexed I/O & Peripheral Pin PC0 (UART, ADC, PWM)
9PC1I/OMultiplexed I/O & Peripheral Pin PC1 (UART, ADC, PWM)
10PC2I/OMultiplexed I/O & Peripheral Pin PC2 (UART, ADC, PWM)
11PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
12VSSAGNDGround Reference Pin (VSSA)
13VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
14PA0 WKUP -I/OMultiplexed I/O & Peripheral Pin PA0 WKUP - (UART, ADC, PWM)
15PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
16PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
17PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
18V_SS4I/OMultiplexed I/O & Peripheral Pin V_SS4 (General)
19V_DD4I/OMultiplexed I/O & Peripheral Pin V_DD4 (General)
20PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC, PWM)
21PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC)
22PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
23PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
24PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC, PWM)
25PC5I/OMultiplexed I/O & Peripheral Pin PC5 (ADC)
26PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
27PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
28PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
29PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, I2C)
30PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C)
31VSS1_GNDGround Reference Pin (VSS1_)
32V_IO1I/OMultiplexed I/O & Peripheral Pin V_IO1 (General)
33PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C, CAN)
34PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM, CAN)
35PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
36PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI)
37PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
38PC7I/OMultiplexed I/O & Peripheral Pin PC7 (PWM)
39PC8I/OMultiplexed I/O & Peripheral Pin PC8 (PWM)
40PC9I/OMultiplexed I/O & Peripheral Pin PC9 (PWM)
41PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, PWM, RTC/CLK)
42PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, PWM)
43PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
44PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, PWM, CAN)
45PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, CAN)
46PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
47VSS2_GNDGround Reference Pin (VSS2_)
48VDD2_PowerPower Supply Input (VDD2_ — 3.3V / 5.0V Standard Logic)
49PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
50PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SPI)
51PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART)
52PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART)
53PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART)
54PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
55PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI)
56PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI)
57PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C)
58PB6I/OMultiplexed I/O & Peripheral Pin PB6 (USB, I2C, PWM)
59PB7I/OMultiplexed I/O & Peripheral Pin PB7 (USB, I2C, PWM)
60BOOT0IInput-Only Pin BOOT0 (General)
61PB8I/OMultiplexed I/O & Peripheral Pin PB8 (PWM)
62PB9I/OMultiplexed I/O & Peripheral Pin PB9 (PWM)
63VSS3_GNDGround Reference Pin (VSS3_)
64V_IO3I/OMultiplexed I/O & Peripheral Pin V_IO3 (General)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
Design note: VBAT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32F203RCT6 (WCH · LQFP-64M(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32F203RCT6 (LQFP-64M(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32F203RCT6 (LQFP-64M(10x10)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32F203RCT6 (LQFP-64M(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32F203RCT6 (LQFP-64M(10x10)) - 4. Package Dimensions (D×E×A)
LQFP-64M(10x10) · 10.00×10.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32F203RCT6 (LQFP-64M(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32F203RCT6 (LQFP-64M(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for CH32F203
P1 · p01_fig01245×131px
CH32F203RCT6 (LQFP-64M(10x10)) — 概述
概述
P16 · p16_fig011438×1322px
CH32F203RCT6 (LQFP-64M(10x10)) — CH32F205_207_203(大容量)数据手册 http://wch.cn
CH32F205_207_203(大容量)数据手册 http://wch.cn
P16 · p16_fig02935×937px
CH32F203RCT6 (LQFP-64M(10x10)) — 3.1.2 连接型F205 CH32F205RBT6
3.1.2 连接型F205 CH32F205RBT6
P16 · p16_fig01P16
CH32F203RCT6 (LQFP-64M(10x10)) — Datasheet Page 16 (p16_fig01)
Datasheet Page 16 (p16_fig01)
P33 · p33_fig011852×852px
CH32F203RCT6 (LQFP-64M(10x10)) — CH32F205_207_203(大容量)数据手册 http://wch.cn
CH32F205_207_203(大容量)数据手册 http://wch.cn
P36 · p36_fig011853×936px
CH32F203RCT6 (LQFP-64M(10x10)) — 图4-4 外部提供低频时钟源电路
图4-4 外部提供低频时钟源电路
P36 · p36_fig021853×933px
CH32F203RCT6 (LQFP-64M(10x10)) — 图4-5 外接8M 晶体典型电路
图4-5 外接8M 晶体典型电路
P36 · p36_fig01P36
CH32F203RCT6 (LQFP-64M(10x10)) — Datasheet Page 36 (p36_fig01)
Datasheet Page 36 (p36_fig01)
P13 · p13_fig011798×1147px
CH32F203RCT6 (LQFP-64M(10x10)) — CH32F203K8T6 [LQFP-48(7x7)]
CH32F203K8T6 [LQFP-48(7x7)]
P13 · p13_fig02656×758px
CH32F203RCT6 (LQFP-64M(10x10)) — PA7/ADC7 17 [LQFP-48(7x7)]
PA7/ADC7 17 [LQFP-48(7x7)]
P20 · p20_fig011405×1244px
CH32F203RCT6 (LQFP-64M(10x10)) — Chapter 3 Pinouts and pin definition [LQFP-100(14x14)]
Chapter 3 Pinouts and pin definition [LQFP-100(14x14)]
P20 · p20_fig02963×963px
CH32F203RCT6 (LQFP-64M(10x10)) — V2.4 18 [LQFP-100(14x14)]
V2.4 18 [LQFP-100(14x14)]
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (CH32F203RCT6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH32F203RCT6 (LQFP-64M(10x10)) is a 64-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, CAN, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-64M(10x10))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, CAN, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — CH32F203 (3)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (LQFP-64M(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-64M(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32F203RCT6 (LQFP-64M(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32F203RCT6 (LQFP-64M(10x10))?

Manufactured by WCH, the CH32F203RCT6 is housed in a LQFP-64M(10x10) package with 64 pins and a 0.50 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)), 2 (PC13 - TAMPER RTC(2) -: Multiplexed I/O & Peripheral Pin PC13 - TAMPER RTC(2) - (RTC/CLK)), 3 (PC14 - OSC32 IN(2)_: Multiplexed I/O & Peripheral Pin PC14 - OSC32 IN(2)_ (RTC/CLK)), 4 (PC15 - OSC32 OUT(2)_: Multiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(2)_ (RTC/CLK)), 5 (OSC_IN: Multiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)), 6 (OSC_OUT: Multiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH32F203RCT6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32F203RCT6 (LQFP-64M(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32F203RCT6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32F203RCT6 (WCH, LQFP-64M(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & CH32F203 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2PC13 - TAMPER RTC(2) -Digital_IOSignal terminal PC13 - TAMPER RTC(2) - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13 - TAMPER RTC(2) -. Supported peripheral buses: RTC/CLK.
3PC14 - OSC32 IN(2)_Digital_IOSignal terminal PC14 - OSC32 IN(2)_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14 - OSC32 IN(2)_. Supported peripheral buses: RTC/CLK.
4PC15 - OSC32 OUT(2)_Digital_IOSignal terminal PC15 - OSC32 OUT(2)_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15 - OSC32 OUT(2)_. Supported peripheral buses: RTC/CLK.
5OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
6OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8PC0Digital_IOSignal terminal PC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0. Supported peripheral buses: UART, ADC, PWM.
9PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: UART, ADC, PWM.
10PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2. Supported peripheral buses: UART, ADC, PWM.
11PC3Digital_IOSignal terminal PC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC.
12VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
13VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14PA0 WKUP -Digital_IOSignal terminal PA0 WKUP - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0 WKUP -. Supported peripheral buses: UART, ADC, PWM.
15PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
16PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
17PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
18V_SS4Digital_IOSignal terminal V_SS4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V_SS4. Supported peripheral buses: General.
19V_DD4Digital_IOSignal terminal V_DD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V_DD4. Supported peripheral buses: General.
20PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, DAC, PWM.
21PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC.
22PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC, PWM.
23PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
24PC4Digital_IOSignal terminal PC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4. Supported peripheral buses: UART, ADC, PWM.
25PC5Digital_IOSignal terminal PC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC.
26PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
27PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
28PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
29PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: UART, I2C.
30PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: UART, I2C.
31VSS1_GND0V electrical ground return terminal (VSS1_) for internal core logic, I/O drivers, and analog sub-blocks.
32V_IO1Digital_IOSignal terminal V_IO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V_IO1. Supported peripheral buses: General.
33PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_NSS, I2C2_SMBA. Supported peripheral buses: UART, SPI, I2C, CAN.
34PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM, CAN.
35PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, PWM.
36PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI.
37PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
38PC7Digital_IOSignal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7. Supported peripheral buses: PWM.
39PC8Digital_IOSignal terminal PC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC8. Supported peripheral buses: PWM.
40PC9Digital_IOSignal terminal PC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC9. Supported peripheral buses: PWM.
41PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, PWM, RTC/CLK.
42PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, PWM.
43PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
44PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: USB, UART, PWM, CAN.
45PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: USB, UART, CAN.
46PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
47VSS2_GND0V electrical ground return terminal (VSS2_) for internal core logic, I/O drivers, and analog sub-blocks.
48VDD2_Power_InPrimary positive power supply input (VDD2_) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
49PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
50PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI3_NSS. Supported peripheral buses: SPI.
51PC10Digital_IOSignal terminal PC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC10. Supported peripheral buses: UART.
52PC11Digital_IOSignal terminal PC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC11. Supported peripheral buses: UART.
53PC12Digital_IOSignal terminal PC12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC12. Supported peripheral buses: UART.
54PD2Digital_IOSignal terminal PD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
55PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: SPI.
56PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: SPI.
57PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C1_SMBA, SPI3_MOSI. Supported peripheral buses: SPI, I2C.
58PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: USB, I2C, PWM.
59PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: USB, I2C, PWM.
60BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
61PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: PWM.
62PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: PWM.
63VSS3_GND0V electrical ground return terminal (VSS3_) for internal core logic, I/O drivers, and analog sub-blocks.
64V_IO3Digital_IOSignal terminal V_IO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V_IO3. Supported peripheral buses: General.
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