Mechanical Dimensions & Land Pattern (FQFN-24-EP(3x4))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
3.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.25 × 0.50 mm
Pins / Total PadsTopology
27P / 27Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit FQFN-24-EP(3x4) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — MIC28513-2YFL-T5 (FQFN-24-EP(3x4))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of MIC28513-2YFL-T5 (FQFN-24-EP(3x4))?
Manufactured by MICROCHIP, the MIC28513-2YFL-T5 is housed in a FQFN-24-EP(3x4) package with 27 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 4.6V to 45V. Key pins include: 1 (DL: Multiplexed I/O & Peripheral Pin DL (General)), 2 (PGND: Ground Reference Pin (PGND)), 3 (DH: Multiplexed I/O & Peripheral Pin DH (General)), 4 (PVIN: Power Supply Input (PVIN — 4.6V to 45V)), 5 (LX: Multiplexed I/O & Peripheral Pin LX (General)), 6 (BST: Multiplexed I/O & Peripheral Pin BST (General)).
What are the IPC-7351B PCB Footprint dimensions for MIC28513-2YFL-T5?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC28513-2YFL-T5 (FQFN-24-EP(3x4)) has a nominal body envelope of 4.00 × 3.00 mm, pitch e = 0.50 mm, and 27 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC28513-2YFL-T5?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC28513-2YFL-T5 (MICROCHIP, FQFN-24-EP(3x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (27 pins) & MIC28513 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | DL | Digital_IO | Signal terminal DL (I/O, 4.6V to 45V domain). Multiplexed alternate functions: DL. Supported peripheral buses: General. |
| 2 | PGND | GND | 0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 3 | DH | Digital_IO | Signal terminal DH (I/O, 4.6V to 45V domain). Multiplexed alternate functions: DH. Supported peripheral buses: General. |
| 4 | PVIN | Power_In | Primary positive power supply input (PVIN) operating in the 4.6V to 45V domain (Max rating: 45.0V). |
| 5 | LX | Digital_IO | Signal terminal LX (I/O, 4.6V to 45V domain). Multiplexed alternate functions: LX. Supported peripheral buses: General. |
| 6 | BST | Digital_IO | Signal terminal BST (I/O, 4.6V to 45V domain). Multiplexed alternate functions: BST. Supported peripheral buses: General. |
| 7 | PVIN | Power_In | Primary positive power supply input (PVIN) operating in the 4.6V to 45V domain (Max rating: 45.0V). |
| 8 | PVIN | Power_In | Primary positive power supply input (PVIN) operating in the 4.6V to 45V domain (Max rating: 45.0V). |
| 9 | PVIN | Power_In | Primary positive power supply input (PVIN) operating in the 4.6V to 45V domain (Max rating: 45.0V). |
| 10 | PGND | GND | 0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 11 | PGND | GND | 0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 12 | SW | Digital_IO | Signal terminal SW (I/O, 4.6V to 45V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General. |
| 13 | AGND | GND | 0V electrical ground return terminal (AGND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 14 | FB | Digital_IO | Signal terminal FB (I/O, 4.6V to 45V domain). Multiplexed alternate functions: FB. Supported peripheral buses: General. |
| 15 | PGOOD | Open_Drain | Signal terminal PGOOD (I/O, 4.6V to 45V domain). Multiplexed alternate functions: PGOOD. Supported peripheral buses: General. |
| 16 | EN | Digital_IO | Chip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset. |
| 17 | V IN | Digital_IO | Signal terminal V IN (I/O, 4.6V to 45V domain). Multiplexed alternate functions: V IN. Supported peripheral buses: General. |
| 18 | I LIM | Digital_IO | Signal terminal I LIM (I/O, 4.6V to 45V domain). Multiplexed alternate functions: I LIM. Supported peripheral buses: General. |
| 19 | VDD | Power_Out | Regulated power output rail (VDD) operating in the 4.6V to 45V domain (Max rating: 45.0V). |
| 20 | P VDD | Power_In | Primary positive power supply input (P VDD) operating in the 4.6V to 45V domain (Max rating: 45.0V). |
| 21 | SW | Digital_IO | Signal terminal SW (I/O, 4.6V to 45V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General. |
| 22 | PGND | GND | 0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 23 | PGND | GND | 0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 24 | FREQ | Digital_IO | Signal terminal FREQ (I/O, 4.6V to 45V domain). Multiplexed alternate functions: FREQ. Supported peripheral buses: General. |
| 25 | PV IN | Digital_IO | Signal terminal PV IN (I/O, 4.6V to 45V domain). Multiplexed alternate functions: PV IN. Supported peripheral buses: General. |
| 26 | PGND | GND | 0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 27 | SW | Digital_IO | Signal terminal SW (I/O, 4.6V to 45V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General. |