![CH395A (LQFP-64M(10x10)) — 3、封装 [LQFP-128(14x14)]](/api/v1/assets/C2685238/extracted/figures/p02_fig01.png)
LQFP-64M(10x10) · 64P
Synchronized Pinout (Symbol / 2D / 3D) (64/64)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 2 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 3 | GND | GND | Ground Reference Pin (GND) |
| 4 | RXP | I/O | Multiplexed I/O & Peripheral Pin RXP (General) |
| 5 | RXN | I/O | Multiplexed I/O & Peripheral Pin RXN (General) |
| 6 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 7 | TXP | I/O | Multiplexed I/O & Peripheral Pin TXP (General) |
| 8 | IO0 | I/O | GPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin) |
| 9 | GND | GND | Ground Reference Pin (GND) |
| 10 | XI | I/O | Multiplexed I/O & Peripheral Pin XI (RTC/CLK) |
| 11 | XO | I/O | Multiplexed I/O & Peripheral Pin XO (RTC/CLK) |
| 12 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 13 | GND | GND | Ground Reference Pin (GND) |
| 14 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 15 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 16 | IO18 | I/O | GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3 |
| 17 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 18 | GND | GND | Ground Reference Pin (GND) |
| 19 | VDDK | Power | Power Supply Input (VDDK — 3.3V / 5.0V Standard Logic) |
| 20 | GND | GND | Ground Reference Pin (GND) |
| 21 | IO10 | I/O | GPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0 |
| 22 | IO11 | I/O | GPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID |
| 23 | IO12 | I/O | GPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK |
| 24 | GPIO2 | I/O | Multiplexed I/O & Peripheral Pin GPIO2 (General) |
| 25 | GPIO3/RDY# | I/O | Multiplexed I/O & Peripheral Pin GPIO3/RDY# (General) |
| 26 | RST | I/O | Multiplexed I/O & Peripheral Pin RST (General) |
| 27 | SEL | I/O | Multiplexed I/O & Peripheral Pin SEL (General) |
| 28 | VDDK | Power | Power Supply Input (VDDK — 3.3V / 5.0V Standard Logic) |
| 29 | VCCIO | Power | Power Supply Input (VCCIO — 3.3V / 5.0V Standard Logic) |
| 30 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 31 | SDI/D6 SDO/RTS/D7 | I/O | Multiplexed I/O & Peripheral Pin SDI/D6 SDO/RTS/D7 (UART) |
| 32 | GPIO4 | I/O | Multiplexed I/O & Peripheral Pin GPIO4 (General) |
| 33 | GPIO5/A0 | I/O | Multiplexed I/O & Peripheral Pin GPIO5/A0 (General) |
| 34 | GPIO6 | I/O | Multiplexed I/O & Peripheral Pin GPIO6 (General) |
| 35 | GPIO7 | I/O | Multiplexed I/O & Peripheral Pin GPIO7 (General) |
| 36 | RSTI | I/O | Multiplexed I/O & Peripheral Pin RSTI (General) |
| 37 | GND | GND | Ground Reference Pin (GND) |
| 38 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 39 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 40 | VCCIO | Power | Power Supply Input (VCCIO — 3.3V / 5.0V Standard Logic) |
| 41 | GND | GND | Ground Reference Pin (GND) |
| 42 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 43 | VDDK | Power | Power Supply Input (VDDK — 3.3V / 5.0V Standard Logic) |
| 44 | GND | GND | Ground Reference Pin (GND) |
| 45 | VCCIO | Power | Power Supply Input (VCCIO — 3.3V / 5.0V Standard Logic) |
| 46 | RD# | I/O | Multiplexed I/O & Peripheral Pin RD# (General) |
| 47 | WR# | I/O | Multiplexed I/O & Peripheral Pin WR# (General) |
| 48 | ELINK# | I/O | Multiplexed I/O & Peripheral Pin ELINK# (General) |
| 49 | INT# | I/O | Multiplexed I/O & Peripheral Pin INT# (General) |
| 50 | PCS# | I/O | Multiplexed I/O & Peripheral Pin PCS# (General) |
| 51 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 52 | EACT# | I/O | Multiplexed I/O & Peripheral Pin EACT# (General) |
| 53 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 54 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 55 | D0 | I/O | Multiplexed I/O & Peripheral Pin D0 (General) |
| 56 | D1 | I/O | Multiplexed I/O & Peripheral Pin D1 (General) |
| 57 | RXD/D2 | I/O | Multiplexed I/O & Peripheral Pin RXD/D2 (UART) |
| 58 | TXD/D3 | I/O | Multiplexed I/O & Peripheral Pin TXD/D3 (UART) |
| 59 | SCS/D4 | I/O | Multiplexed I/O & Peripheral Pin SCS/D4 (General) |
| 60 | SCK/D5 | I/O | Multiplexed I/O & Peripheral Pin SCK/D5 (SPI) |
| 61 | SDI/D6 | I/O | Multiplexed I/O & Peripheral Pin SDI/D6 (General) |
| 62 | SDO/D7 | I/O | Multiplexed I/O & Peripheral Pin SDO/D7 (General) |
| 63 | VCCIO | Power | Power Supply Input (VCCIO — 3.3V / 5.0V Standard Logic) |
| 64 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
PIN 1 NC
I/OMultiplexed I/O & Peripheral Pin NC (General)
Design note: Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-64M(10x10) · 10.00×10.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for CH395
P1 · p01_fig011751×1163px
P1 · p01_fig02240×254px
P3 · p03_fig011537×796px
P3 · p03_fig021536×1524px
P4 · p04_fig011736×2216px
P42 · p42_fig011441×1165px
P42 · p42_fig021376×781px
P43 · p43_fig011653×1852px
P43 · p43_fig01P43
P44 · p44_fig011730×2230px
P2 · p02_fig011670×1659px
Technical Specifications & Part Details (CH395A)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH395A (LQFP-64M(10x10)) is a 64-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-64M(10x10))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol64 auto-grouped pins
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH395 (3)
LQFP-128(14x14) · 128P
LQFP-128(14x14) · 128P
Mechanical Dimensions & Land Pattern (LQFP-64M(10x10))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-64M(10x10) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH395A (LQFP-64M(10x10))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH395A (LQFP-64M(10x10))?
Manufactured by WCH, the CH395A is housed in a LQFP-64M(10x10) package with 64 pins and a 0.50 mm lead pitch. Key pins include: 1 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 2 (VCC33: Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)), 3 (GND: Ground Reference Pin (GND)), 4 (RXP: Multiplexed I/O & Peripheral Pin RXP (General)), 5 (RXN: Multiplexed I/O & Peripheral Pin RXN (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).
What are the IPC-7351B PCB Footprint dimensions for CH395A?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH395A (LQFP-64M(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH395A?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH395A (WCH, LQFP-64M(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (64 pins) & CH395 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 2 | VCC33 | Power_In | Primary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 3 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 4 | RXP | Digital_IO | Signal terminal RXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXP. Supported peripheral buses: General. |
| 5 | RXN | Digital_IO | Signal terminal RXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXN. Supported peripheral buses: General. |
| 6 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 7 | TXP | Digital_IO | Signal terminal TXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXP. Supported peripheral buses: General. |
| 8 | IO0 | Digital_IO | GPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin) |
| 9 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 10 | XI | Digital_IO | Signal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK. |
| 11 | XO | Digital_IO | Signal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK. |
| 12 | VCC33 | Power_In | Primary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 13 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 14 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 15 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 16 | IO18 | Digital_IO | GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3 |
| 17 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 18 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 19 | VDDK | Power_In | Primary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 20 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 21 | IO10 | Digital_IO | GPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0 |
| 22 | IO11 | Digital_IO | GPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID |
| 23 | IO12 | Digital_IO | GPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK |
| 24 | GPIO2 | Digital_IO | Signal terminal GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General. |
| 25 | GPIO3/RDY# | Digital_IO | Signal terminal GPIO3/RDY# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO3/RDY#. Supported peripheral buses: General. |
| 26 | RST | Digital_IO | Signal terminal RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST. Supported peripheral buses: General. |
| 27 | SEL | Digital_IO | Signal terminal SEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEL. Supported peripheral buses: General. |
| 28 | VDDK | Power_In | Primary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 29 | VCCIO | Power_In | Primary positive power supply input (VCCIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 30 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 31 | SDI/D6 SDO/RTS/D7 | Digital_IO | Signal terminal SDI/D6 SDO/RTS/D7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDI/D6 SDO/RTS/D7. Supported peripheral buses: UART. |
| 32 | GPIO4 | Digital_IO | Signal terminal GPIO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO4. Supported peripheral buses: General. |
| 33 | GPIO5/A0 | Digital_IO | Signal terminal GPIO5/A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO5/A0. Supported peripheral buses: General. |
| 34 | GPIO6 | Digital_IO | Signal terminal GPIO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO6. Supported peripheral buses: General. |
| 35 | GPIO7 | Digital_IO | Signal terminal GPIO7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO7. Supported peripheral buses: General. |
| 36 | RSTI | Digital_IO | Signal terminal RSTI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTI. Supported peripheral buses: General. |
| 37 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 38 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 39 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 40 | VCCIO | Power_In | Primary positive power supply input (VCCIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 41 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 42 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 43 | VDDK | Power_In | Primary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 44 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 45 | VCCIO | Power_In | Primary positive power supply input (VCCIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 46 | RD# | Digital_IO | Signal terminal RD# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RD#. Supported peripheral buses: General. |
| 47 | WR# | Digital_IO | Signal terminal WR# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WR#. Supported peripheral buses: General. |
| 48 | ELINK# | Digital_IO | Signal terminal ELINK# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ELINK#. Supported peripheral buses: General. |
| 49 | INT# | Digital_IO | Signal terminal INT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT#. Supported peripheral buses: General. |
| 50 | PCS# | Digital_IO | Signal terminal PCS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PCS#. Supported peripheral buses: General. |
| 51 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 52 | EACT# | Digital_IO | Signal terminal EACT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EACT#. Supported peripheral buses: General. |
| 53 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 54 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 55 | D0 | Digital_IO | Signal terminal D0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D0. Supported peripheral buses: General. |
| 56 | D1 | Digital_IO | Signal terminal D1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D1. Supported peripheral buses: General. |
| 57 | RXD/D2 | Digital_IO | Signal terminal RXD/D2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD/D2. Supported peripheral buses: UART. |
| 58 | TXD/D3 | Digital_IO | Signal terminal TXD/D3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD/D3. Supported peripheral buses: UART. |
| 59 | SCS/D4 | Digital_IO | Signal terminal SCS/D4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS/D4. Supported peripheral buses: General. |
| 60 | SCK/D5 | Digital_IO | Signal terminal SCK/D5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCK/D5. Supported peripheral buses: SPI. |
| 61 | SDI/D6 | Digital_IO | Signal terminal SDI/D6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDI/D6. Supported peripheral buses: General. |
| 62 | SDO/D7 | Digital_IO | Signal terminal SDO/D7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDO/D7. Supported peripheral buses: General. |
| 63 | VCCIO | Power_In | Primary positive power supply input (VCCIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 64 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |