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PIC16F917-I/P (DIP-40) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC16F917-I/P

MICROCHIPID: C50405DIP-40 · 40 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC16F917-I/P (DIP-40)1MCLR/VPP2RA0/AN0/C1-/3RA1/AN1/C2-/4RA2/AN2/C2+/5IO26RA4/C1OUT/T07RA5/AN4/C2OU8RE0/AN5/SEG29RE1/AN6/SEG210RE2/AN7/SEG211VDD12VSS13RA7/OSC1/CLK14RA6/OSC2/CLK15RC0/VLCD116RC1/VLCD217RC2/VLCD318RC3/SEG619RD0/COM320RD140ICDDATA39ICDCLK38RB5/COM137RB4/COM036RB3/SEG335RB2/SEG234RB1/SEG133RB0/INT/SEG032VDD31VSS30RD7/SEG2029RD6/SEG1928RD5/SEG1827RD4/SEG1726RC7/RX/DT/SD25RC6/TX/CK/SC24RC5/T1CKI/CC23RC4/T1G/SDO/22RD3/SEG1621RD2/CCP2Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.830.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940E=13.74mm · Pitch e=2.54mmD=50.26mm-22-20-18-16-14-12-10-8-6-4-2024681012141618202239373533312927252321191715131197531-1-3-5-7-9-11-13-15-17-19-21-23-25-27-29-31-33-35-37-39mm
3. 3D CAD MODEL
Package Body: 13.74mm × 50.26mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (40/40)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1MCLR/VPPI/OMultiplexed I/O & Peripheral Pin MCLR/VPP (General)
2RA0/AN0/C1-/SEG12I/OMultiplexed I/O & Peripheral Pin RA0/AN0/C1-/SEG12 (General)
3RA1/AN1/C2-/SEG7I/OMultiplexed I/O & Peripheral Pin RA1/AN1/C2-/SEG7 (General)
4RA2/AN2/C2+/VREF-/COM2AnalogMultiplexed I/O & Peripheral Pin RA2/AN2/C2+/VREF-/COM2 (General)
5IO2I/OGPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1
6RA4/C1OUT/T0CKI/SEG4I/OMultiplexed I/O & Peripheral Pin RA4/C1OUT/T0CKI/SEG4 (General)
7RA5/AN4/C2OUT/SS/SEG5I/OMultiplexed I/O & Peripheral Pin RA5/AN4/C2OUT/SS/SEG5 (General)
8RE0/AN5/SEG21I/OMultiplexed I/O & Peripheral Pin RE0/AN5/SEG21 (General)
9RE1/AN6/SEG22I/OMultiplexed I/O & Peripheral Pin RE1/AN6/SEG22 (General)
10RE2/AN7/SEG23I/OMultiplexed I/O & Peripheral Pin RE2/AN7/SEG23 (General)
11VDDPowerPower Supply Input (VDD — 2.0V-5.5V)
12VSSGNDGround Reference Pin (VSS)
13RA7/OSC1/CLKIN/T1OSII/OMultiplexed I/O & Peripheral Pin RA7/OSC1/CLKIN/T1OSI (RTC/CLK)
14RA6/OSC2/CLKOUT/T1OSOI/OMultiplexed I/O & Peripheral Pin RA6/OSC2/CLKOUT/T1OSO (RTC/CLK)
15RC0/VLCD1I/OMultiplexed I/O & Peripheral Pin RC0/VLCD1 (General)
16RC1/VLCD2I/OMultiplexed I/O & Peripheral Pin RC1/VLCD2 (General)
17RC2/VLCD3I/OMultiplexed I/O & Peripheral Pin RC2/VLCD3 (General)
18RC3/SEG6I/OMultiplexed I/O & Peripheral Pin RC3/SEG6 (General)
19RD0/COM3I/OMultiplexed I/O & Peripheral Pin RD0/COM3 (General)
20RD1I/OMultiplexed I/O & Peripheral Pin RD1 (General)
21RD2/CCP2I/OMultiplexed I/O & Peripheral Pin RD2/CCP2 (General)
22RD3/SEG16I/OMultiplexed I/O & Peripheral Pin RD3/SEG16 (General)
23RC4/T1G/SDO/SEG11I/OMultiplexed I/O & Peripheral Pin RC4/T1G/SDO/SEG11 (General)
24RC5/T1CKI/CCP1/SEG10I/OMultiplexed I/O & Peripheral Pin RC5/T1CKI/CCP1/SEG10 (General)
25RC6/TX/CK/SCK/SCL/SEG9I/OMultiplexed I/O & Peripheral Pin RC6/TX/CK/SCK/SCL/SEG9 (SPI, I2C)
26RC7/RX/DT/SDI/SDA/SEG8I/OMultiplexed I/O & Peripheral Pin RC7/RX/DT/SDI/SDA/SEG8 (I2C)
27RD4/SEG17I/OMultiplexed I/O & Peripheral Pin RD4/SEG17 (General)
28RD5/SEG18I/OMultiplexed I/O & Peripheral Pin RD5/SEG18 (General)
29RD6/SEG19I/OMultiplexed I/O & Peripheral Pin RD6/SEG19 (General)
30RD7/SEG20I/OMultiplexed I/O & Peripheral Pin RD7/SEG20 (General)
31VSSGNDGround Reference Pin (VSS)
32VDDPowerPower Supply Input (VDD — 2.0V-5.5V)
33RB0/INT/SEG0I/OMultiplexed I/O & Peripheral Pin RB0/INT/SEG0 (General)
34RB1/SEG1I/OMultiplexed I/O & Peripheral Pin RB1/SEG1 (General)
35RB2/SEG2I/OMultiplexed I/O & Peripheral Pin RB2/SEG2 (General)
36RB3/SEG3I/OMultiplexed I/O & Peripheral Pin RB3/SEG3 (General)
37RB4/COM0I/OMultiplexed I/O & Peripheral Pin RB4/COM0 (General)
38RB5/COM1I/OMultiplexed I/O & Peripheral Pin RB5/COM1 (General)
39ICDCLKI/OMultiplexed I/O & Peripheral Pin ICDCLK (General)
40ICDDATAI/OMultiplexed I/O & Peripheral Pin ICDDATA (General)
PIN 1 MCLR/VPP
I/O
Multiplexed I/O & Peripheral Pin MCLR/VPP (General)
Design note: Programmingvoltage
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC16F917-I/P (MICROCHIP · DIP-40)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC16F917-I/P (DIP-40) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC16F917-I/P (DIP-40) - 2. Standard Pinout (Top View)
True package pinout (40 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC16F917-I/P (DIP-40) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC16F917-I/P (DIP-40) - 4. Package Dimensions (D×E×A)
DIP-40 · 13.74×50.26mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC16F917-I/P (DIP-40) - 5. Recommended Land Pattern
IPC-7351B Footprint (40 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC16F917-I/P (DIP-40) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for PIC16F917
P2 · p02_fig011777×1639px
PIC16F917-I/P (DIP-40) — DS41250F-page ii © 2007 Microchip Technology Inc. | Trademarks | SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. | All other trademarks mentioned herein are property of their respective companies. | © 2007, Microch
DS41250F-page ii © 2007 Microchip Technology Inc. | Trademarks | SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. | All other trademarks mentioned herein are property of their respective companies. | © 2007, Microch
P2 · p02_fig02782×281px
PIC16F917-I/P (DIP-40) — DS41250F-page ii © 2007 Microchip Technology Inc.
DS41250F-page ii © 2007 Microchip Technology Inc.
P199 · p199_fig011777×938px
PIC16F917-I/P (DIP-40) — FIGURE 14-2: SPI MASTER/SLAVE CONNECTION
FIGURE 14-2: SPI MASTER/SLAVE CONNECTION
P206 · p206_fig011731×641px
PIC16F917-I/P (DIP-40) — FIGURE 14-8: I2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 14-8: I2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P206 · p206_fig01P206
PIC16F917-I/P (DIP-40) — Datasheet Page 206 (p206_fig01)
Datasheet Page 206 (p206_fig01)
P207 · p207_fig011777×2496px
PIC16F917-I/P (DIP-40) — FIGURE 14-9: I2C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)
FIGURE 14-9: I2C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)
P215 · p215_fig011753×625px
PIC16F917-I/P (DIP-40) — FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
P216 · p216_fig01867×847px
PIC16F917-I/P (DIP-40) — FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM
FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM
P307 · p307_fig01All Packages in PDF
PIC16F917-I/P (DIP-40) — 21.1 Package Marking Information
21.1 Package Marking Information
P312 · p312_fig01All Packages in PDF
PIC16F917-I/P (DIP-40) — DS41250F-page 310 © 2007 Microchip Technology Inc. | 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN] | Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.m
DS41250F-page 310 © 2007 Microchip Technology Inc. | 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN] | Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.m
P313 · p313_fig01All Packages in PDF
PIC16F917-I/P (DIP-40) — © 2007 Microchip Technology Inc. DS41250F-page 311 | 28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] | Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microc
© 2007 Microchip Technology Inc. DS41250F-page 311 | 28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] | Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microc

Technical Specifications & Part Details (PIC16F917-I/P)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC16F917-I/P (DIP-40) is a 40-pin standard electronic & interconnect component featuring a 50.26 × 13.74 × 4.00 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 2.0V-5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C, PWM, RTC/CLK, SPI interfaces.
Operating Supply VoltageV_CC / V_DD
2.0V-5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
50.26 × 13.74 × 4.00 mm (A1=0.51 mm)
Package family: DIP (DIP-40)
Pin Count & Lead PitchN / e
40 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C, PWM, RTC/CLK, SPI
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol40 auto-grouped pins
OK
IPC-7351B Land Pattern40 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (DIP-40)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
50.26 × 13.74 mm
Height (A) & Pitch (e)IPC-7351B
A=4.00mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
40P / 40Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
DIP-40
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16F917-I/P (DIP-40)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16F917-I/P (DIP-40)?

Manufactured by MICROCHIP, the PIC16F917-I/P is housed in a DIP-40 package with 40 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 2.0V-5.5V. Key pins include: 1 (MCLR/VPP: Multiplexed I/O & Peripheral Pin MCLR/VPP (General)), 2 (RA0/AN0/C1-/SEG12: Multiplexed I/O & Peripheral Pin RA0/AN0/C1-/SEG12 (General)), 3 (RA1/AN1/C2-/SEG7: Multiplexed I/O & Peripheral Pin RA1/AN1/C2-/SEG7 (General)), 4 (RA2/AN2/C2+/VREF-/COM2: Multiplexed I/O & Peripheral Pin RA2/AN2/C2+/VREF-/COM2 (General)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (RA4/C1OUT/T0CKI/SEG4: Multiplexed I/O & Peripheral Pin RA4/C1OUT/T0CKI/SEG4 (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16F917-I/P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F917-I/P (DIP-40) has a nominal body envelope of 13.74 × 50.26 mm, pitch e = 2.54 mm, and 40 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F917-I/P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F917-I/P (MICROCHIP, DIP-40) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (40 pins) & PIC16F917 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1MCLR/VPPDigital_IOSignal terminal MCLR/VPP (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: MCLR/VPP. Supported peripheral buses: General.
2RA0/AN0/C1-/SEG12Digital_IOSignal terminal RA0/AN0/C1-/SEG12 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RA0/AN0/C1-/SEG12. Supported peripheral buses: General.
3RA1/AN1/C2-/SEG7Digital_IOSignal terminal RA1/AN1/C2-/SEG7 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RA1/AN1/C2-/SEG7. Supported peripheral buses: General.
4RA2/AN2/C2+/VREF-/COM2AnalogSignal terminal RA2/AN2/C2+/VREF-/COM2 (Analog, 2.0V-5.5V domain). Multiplexed alternate functions: RA2/AN2/C2+/VREF-/COM2. Supported peripheral buses: General.
5IO2Digital_IOGPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1
6RA4/C1OUT/T0CKI/SEG4Digital_IOSignal terminal RA4/C1OUT/T0CKI/SEG4 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RA4/C1OUT/T0CKI/SEG4. Supported peripheral buses: General.
7RA5/AN4/C2OUT/SS/SEG5Digital_IOSignal terminal RA5/AN4/C2OUT/SS/SEG5 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RA5/AN4/C2OUT/SS/SEG5. Supported peripheral buses: General.
8RE0/AN5/SEG21Digital_IOSignal terminal RE0/AN5/SEG21 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RE0/AN5/SEG21. Supported peripheral buses: General.
9RE1/AN6/SEG22Digital_IOSignal terminal RE1/AN6/SEG22 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RE1/AN6/SEG22. Supported peripheral buses: General.
10RE2/AN7/SEG23Digital_IOSignal terminal RE2/AN7/SEG23 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RE2/AN7/SEG23. Supported peripheral buses: General.
11VDDPower_InPrimary positive power supply input (VDD) operating in the 2.0V-5.5V domain (Max rating: 5.5V).
12VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
13RA7/OSC1/CLKIN/T1OSIDigital_IOSignal terminal RA7/OSC1/CLKIN/T1OSI (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RA7/OSC1/CLKIN/T1OSI. Supported peripheral buses: RTC/CLK.
14RA6/OSC2/CLKOUT/T1OSODigital_IOSignal terminal RA6/OSC2/CLKOUT/T1OSO (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RA6/OSC2/CLKOUT/T1OSO. Supported peripheral buses: RTC/CLK.
15RC0/VLCD1Digital_IOSignal terminal RC0/VLCD1 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC0/VLCD1. Supported peripheral buses: General.
16RC1/VLCD2Digital_IOSignal terminal RC1/VLCD2 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC1/VLCD2. Supported peripheral buses: General.
17RC2/VLCD3Digital_IOSignal terminal RC2/VLCD3 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC2/VLCD3. Supported peripheral buses: General.
18RC3/SEG6Digital_IOSignal terminal RC3/SEG6 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC3/SEG6. Supported peripheral buses: General.
19RD0/COM3Digital_IOSignal terminal RD0/COM3 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RD0/COM3. Supported peripheral buses: General.
20RD1Digital_IOSignal terminal RD1 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RD1. Supported peripheral buses: General.
21RD2/CCP2Digital_IOSignal terminal RD2/CCP2 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RD2/CCP2. Supported peripheral buses: General.
22RD3/SEG16Digital_IOSignal terminal RD3/SEG16 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RD3/SEG16. Supported peripheral buses: General.
23RC4/T1G/SDO/SEG11Digital_IOSignal terminal RC4/T1G/SDO/SEG11 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC4/T1G/SDO/SEG11. Supported peripheral buses: General.
24RC5/T1CKI/CCP1/SEG10Digital_IOSignal terminal RC5/T1CKI/CCP1/SEG10 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC5/T1CKI/CCP1/SEG10. Supported peripheral buses: General.
25RC6/TX/CK/SCK/SCL/SEG9Digital_IOSignal terminal RC6/TX/CK/SCK/SCL/SEG9 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC6/TX/CK/SCK/SCL/SEG9. Supported peripheral buses: SPI, I2C.
26RC7/RX/DT/SDI/SDA/SEG8Digital_IOSignal terminal RC7/RX/DT/SDI/SDA/SEG8 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC7/RX/DT/SDI/SDA/SEG8. Supported peripheral buses: I2C.
27RD4/SEG17Digital_IOSignal terminal RD4/SEG17 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RD4/SEG17. Supported peripheral buses: General.
28RD5/SEG18Digital_IOSignal terminal RD5/SEG18 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RD5/SEG18. Supported peripheral buses: General.
29RD6/SEG19Digital_IOSignal terminal RD6/SEG19 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RD6/SEG19. Supported peripheral buses: General.
30RD7/SEG20Digital_IOSignal terminal RD7/SEG20 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RD7/SEG20. Supported peripheral buses: General.
31VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32VDDPower_InPrimary positive power supply input (VDD) operating in the 2.0V-5.5V domain (Max rating: 5.5V).
33RB0/INT/SEG0Digital_IOSignal terminal RB0/INT/SEG0 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RB0/INT/SEG0. Supported peripheral buses: General.
34RB1/SEG1Digital_IOSignal terminal RB1/SEG1 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RB1/SEG1. Supported peripheral buses: General.
35RB2/SEG2Digital_IOSignal terminal RB2/SEG2 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RB2/SEG2. Supported peripheral buses: General.
36RB3/SEG3Digital_IOSignal terminal RB3/SEG3 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RB3/SEG3. Supported peripheral buses: General.
37RB4/COM0Digital_IOSignal terminal RB4/COM0 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RB4/COM0. Supported peripheral buses: General.
38RB5/COM1Digital_IOSignal terminal RB5/COM1 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RB5/COM1. Supported peripheral buses: General.
39ICDCLKDigital_IOSignal terminal ICDCLK (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: ICDCLK. Supported peripheral buses: General.
40ICDDATADigital_IOSignal terminal ICDDATA (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: ICDDATA. Supported peripheral buses: General.
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