DFN-10(3x3) · 11P
Synchronized Pinout (Symbol / 2D / 3D) (11/11)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | VDD33 | Power | Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic) |
| 2 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (UART, I2C, SWD/JTAG) |
| 3 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (UART, I2C, SWD/JTAG) |
| 4 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (UART, SPI, PWM) |
| 5 | PA7/T4/TMR | I/O | Multiplexed I/O & Peripheral Pin PA7/T4/TMR (General) |
| 6 | XI | I/O | Multiplexed I/O & Peripheral Pin XI (RTC/CLK) |
| 7 | GND | GND | Ground Reference Pin (GND) |
| 8 | V5 | I/O | Multiplexed I/O & Peripheral Pin V5 (General) |
| 9 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (UART, I2C) |
| 10 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (UART, I2C, PWM) |
| 11 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (UART, SWD/JTAG) |
PIN 1 VDD33
PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
Design note: 如果是单 一3 .3V电源供电 ，则VDD33引脚输入额定3 .3V 电源 V5引脚悬空或与VDD33引脚短接 ， 。
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (11 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
DFN-10(3x3) · 3.00×3.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (11 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH570 / CH572
P1 · p01_fig01247×133px
P3 · p03_fig011459×1448px
P3 · p03_fig02893×576px
P4 · p04_fig011266×490px
P4 · p04_fig021462×1943px
P4 · p04_fig01P4
P44 · p44_fig011680×312px
P44 · p44_fig021713×2342px
P44 · p44_fig01P44
Technical Specifications & Part Details (CH570Q)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH570Q (DFN-10(3x3)) is a 10-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, SPI, I2C, PWM, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
16MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: DFN (DFN-10(3x3))
Pin Count & Lead PitchN / e
10 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, SPI, I2C, PWM, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol11 auto-grouped pins
IPC-7351B Land Pattern11 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteEPAD 2.50×1.60mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH570 / CH572 (3)
DFN-10-EP(3x3) · 11P
QFN-20-EP(3x3) · 21P
Mechanical Dimensions & Land Pattern (DFN-10(3x3))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.25 × 0.65 mm
Pins / Total PadsTopology
11P / 11Pad (DUAL_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit DFN-10(3x3) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH570Q (DFN-10(3x3))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH570Q (DFN-10(3x3))?
Manufactured by WCH, the CH570Q is housed in a DFN-10(3x3) package with 11 pins and a 0.50 mm lead pitch. Key pins include: 1 (VDD33: Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)), 2 (PA0: Multiplexed I/O & Peripheral Pin PA0 (UART, I2C, SWD/JTAG)), 3 (PA1: Multiplexed I/O & Peripheral Pin PA1 (UART, I2C, SWD/JTAG)), 4 (PA7: Multiplexed I/O & Peripheral Pin PA7 (UART, SPI, PWM)), 5 (PA7/T4/TMR: Multiplexed I/O & Peripheral Pin PA7/T4/TMR (General)), 6 (XI: Multiplexed I/O & Peripheral Pin XI (RTC/CLK)).
What are the IPC-7351B PCB Footprint dimensions for CH570Q?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH570Q (DFN-10(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 11 copper pads plus a central exposed thermal pad (EPAD) of 2.50 × 1.60 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH570Q?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH570Q (WCH, DFN-10(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (11 pins) & CH570 / CH572 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VDD33 | Power_In | Primary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 2 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, I2C, SWD/JTAG. |
| 3 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, I2C, SWD/JTAG. |
| 4 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: UART, SPI, PWM. |
| 5 | PA7/T4/TMR | Digital_IO | Signal terminal PA7/T4/TMR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7/T4/TMR. Supported peripheral buses: General. |
| 6 | XI | Digital_IO | Signal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK. |
| 7 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 8 | V5 | Digital_IO | Signal terminal V5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V5. Supported peripheral buses: General. |
| 9 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, I2C. |
| 10 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, I2C, PWM. |
| 11 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, SWD/JTAG. |